January 2007
Latest update adds support for LatticeECP2M20 device and 32-bit embedded processor ports to LatticeSC/M and LatticeXP families.
ispLEVER 6.1 is the latest release of design tools from Lattice. We’re committed to continuously improving the programmable logic design experience, and ispLEVER 6.1 is part of that commitment. Packed with new time-saving features, support for the latest devices, and general improvements to existing tools, ispLEVER 6.1 gives you "More of the Best" from Lattice.
Probably the most notable improvement in ispLEVER 6.1 is the introduction of the LatticeECP2M and LatticeSC/M FPGA products. The LatticeECP2M was recently named Electronic Products 2006 Product of the Year, and for good reason – with a perfect balance of performance/features vs. value, the LatticeECP2M is winning the favor of designers all around the world in all kinds of applications.
The LatticeSC FPGA family is designed to go a step further to meet the needs of today’s highest-performance applications. The LatticeSCM adds dedicated high-performance structured ASIC blocks to efficiently implement popular high-speed communications functionality. All of these families are first introduced in the ispLEVER 6.1 tools. Support for additional members of the LatticeECP2M family is included in Service Pack 1.
Along with ispLEVER 6.1, we have released the LatticeMico32 System tools. You can read more about LatticeMico32 System tools elsewhere in this newsletter. But briefly, this is a microprocessor design environment, where you can easily define just how you’d like the various peripheral components of the LatticeMico32 to be configured. Along with the Service Pack 1 release, we’ve updated the LatticeMico System tools again – adding support to target the LatticeSC/M, LatticeXP, and adding peripherals like an interface to the Tri-Speed Ethernet Media Access Controller IP core.
MicoSystem Builder (MSB) Interface
We’re very excited about the inclusion of a brand new design tool in ispLEVER 6.1 – HDL Explorer. This innovative tool helps you visualize, analyze, document and debug HDL designs. HDL Explorer generates graphic representations of your design’s hierarchical structure and connectivity. You can view your design in a variety of graphical and hierarchical formats, and use intelligent tools to cross-probe between views and pinpoint problems.
HDL Explorer is particularly useful for IP integration, and maintenance, and re-engineering of complex FPGA HDL designs, which require a comprehensive and in-depth approach to design analysis and management. With HDL Explorer, you can see higher-level abstractions of the design structure than traditional simulator or synthesis tools. This helps you create and manage documentation and analyze design structure, greatly reducing the amount of design time devoted to these tasks.
HDL Explorer
ispLEVER 6.1 is also packed with numerous improvements to the existing tool set, updated 3rd party tools, and more. To see the full list, check the ispLEVER help, or visit this link:
http://www.latticesemi.com/products/designsoftware/isplever/whatsnew.cfm
If you haven’t yet invested in the ispLEVER tools, here’s one more incentive – each new shipment of ispLEVER for Windows now includes a Lattice USB download cable. Once you finish your design and need to program some hardware, we're sure you'll need one anyway, so we’re giving you a jump start!
© Lattice Semiconductor Corporation 2012
