January 2007
IPexpress cores for LatticeECP2M take advantage of increased memory, DSP blocks and SERDES channels, enabling higher performance with low-cost design implementation.
Lattice recently introduced the LatticeECP2M device family, the industry's first high-volume FPGA that includes both high-speed SERDES and an embedded Physical Coding Sublayer. The combination of a low-cost FPGA fabric with an embedded high-speed serial interface has proven to be a winning feature set to customers, especially those designing with SERDES for the first time. For many high-speed interfaces, such as PCI Express, Lattice provides IPexpress User-Configurable IP cores, reducing learning curves and enabling designers' quick adoption of these interfaces. LatticeECP2M also includes substantial increases in sysDSP and embedded memory block resources, which enable improved performance for many DSP applications. As a result, several DSP IP cores have also been enhanced to take advantage of these features.
The IPexpress User-Configurable IP core portfolio has increased substantially to support LatticeECP2M. Several other device families have also been updated with IPexpress support as well. The following table outlines the availability today:
| Communications | LatticeSC | LatticeECP2M | LatticeECP2 | LatticeEC/ECP | LatticeXP |
|---|---|---|---|---|---|
| 10Gigabit Ethernet MAC |  |
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| CPRI | |
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| OBSAI RP3 | |
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| SGMII | |
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| SPI4.2 | |
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| Triple Speed Ethernet MAC | |
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| Connectivity | |||||
| PCI Express x1 Endpoint | |
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| 32-Bit PCI Master/Target & 32-Bit PCI Target (33 & 66 MHz) |
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| 64-Bit PCI Master/Target & 64-Bit PCI Target (33 & 66 MHz) | |
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| Digital Signal Processing | |||||
| Block Convolutional Encoder | |
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| Block Viterbi Decoder | |
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| Cascaded Integrator-Comb (CIC) | |
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| Color Space Converter | |
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| Correlator | |
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| Distributed Arithmetic FIR (DA-FIR) | |
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| Dynamic Block Reed-Solomon Encoder/Decoder | |
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| FFT Compiler | |
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| FIR Filter Generator | |
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| Interleaver/De-Interleaver | |
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| Numerically Controlled Oscillator | |
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| Turbo Encoder/Decoder | |
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| Processor, Controller & Peripheral Cores | |||||
| DDR SDRAM Controller - Pipelined | |
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| DDR2 SDRAM Controller - Pipelined | |
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| LatticeMico32 | |
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| LatticeMico8 | |
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| Soft Error Detection | |
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As a reminder, all IPexpress User-Configurable IP cores available for download are visible on the Lattice IP Server tab in the ispLEVER IPexpress GUI window.
Lattice has also introduced "bundles" of IP known as IP Suites, which offer users a new way to purchase IP from Lattice. IP Suites are packages of IP cores that help you quickly develop some of today's hottest applications. Each suite includes a collection of ispLeverCOREs that can be targeted to a number of Lattice FPGA families. You can use and re-use any of the included IP cores as much as you like during the license period. IP Suites are an exciting new way to help you realize the flexibility and value of IP solutions from Lattice.
The IP Suites comprise basic to advanced IP cores, including fundamental DSP cores such as:
The suites cover a full range of applications including embedded computing, wireless and wireline communications, networking, video/imaging, low-power applications, and many others.
| MachXO | LatticeXP | LatticeECP/EC | LatticeECP2/M | LatticeSC | |
|---|---|---|---|---|---|
| IP Value Suite | |||||
| DDR Controller | |
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| DDR2 Controller | |
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| FFT Compiler | |
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| FIR Filter | |
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| Tri-Speed MAC | |
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| System Design IP Suite | |||||
| DDR Controller | |
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| DDR2 Controller | |
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| PCI Master/Target 32-bit | |
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| PCI Target 32-bit | |
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| PCI Express x1 | |
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| WiMAX Design IP Suite | |||||
| Block Convolutional Encoder | |
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| Block Viterbi Decoder | |
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| Dynamic Block RS Decoder | |
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| Dynamic Block RS Encoder | |
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| FFT Compiler | |
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| Interleaver/De-Interleaver | |
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| DSP Design IP Suite | |||||
| CIC Filter | |
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| DA-FIR Filter | |
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| FFT Compiler | |
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| FIR Filter | |
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| Num. Cont. Oscillator (NCO) | |
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| 1 GbE Design IP Suite | |||||
| DDR Controller | |
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| DDR2 Controller | |
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| SGMII | |
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| Tri-Speed MAC | |
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| 10 GbE Design IP Suite | |||||
| 10 GbE MAC | |
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| DDR Controller | |
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| DDR2 Controller | |
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| SPI-4.2 | |
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© Lattice Semiconductor Corporation 2012
