January 2007
New 90nm LatticeECP2M FPGAs First to Offer Embedded SERDES
The LatticeECP2M family redefines the low-cost FPGA category, with "More of the Best" FPGA features for less.
Lattice recently rolled out the LatticeECP2M FPGA family, the industry's first low cost FPGAs offering high-speed embedded SERDES I/O plus a pre-engineered Physical Coding Sublayer (PCS) block. Based on the innovative LatticeECP2 low cost architecture, the new LatticeECP2M family has been developed on advanced 90nm CMOS technology utilizing 300mm wafers.
Previously, high-speed embedded SERDES serial I/O with speeds over 3Gbps have been available only on relatively expensive high-end FPGAs. Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video, and industrial equipment. Priced at approximately one-third the cost of competitive SERDES-based FPGAs, the LatticeECP2M FPGA family effectively bridges the price/performance gap between low-cost and high-end FPGAs.
| Device | ECP2M20 | ECP2M35 | ECP2M50 | ECP2M70 | ECP2M100 |
|---|---|---|---|---|---|
| LUTs (K) | 19 | 34 | 48 | 67 | 95 |
| sysMEM™ Blocks (18kb) | 66 | 114 | 225 | 246 | 288 |
| Embedded Memory (Kbits) | 1217 | 2101 | 4147 | 4534 | 5308 |
| Distributed Memory (Kbits) | 41 | 71 | 101 | 145 | 202 |
| sysDSP™ Blocks | 6 | 8 | 22 | 24 | 42 |
| 18x18 Multipliers | 24 | 32 | 88 | 96 | 168 |
| SPLL+GPLL+DLL | 2+6+2 | 2+6+2 | 2+6+2 | 2+6+2 | 2+6+2 |
| Packages & SERDES / I/O Combinations | |||||
| 256 fpBGA (17 x 17 mm) | 4/140 | 4/140 | |||
| 484 fpBGA (23 x 23 mm) | 4/304 | 4/303 | 4/270 | ||
| 672 fpBGA (27 x 27 mm) | 4/410 | 8/381 | |||
| 900 fpBGA (31 x 31 mm) | 8/438 | 16/452 | 16/452 | ||
| 1156 fpBGA (35 x 35 mm) | 16/616 | ||||
The LatticeECP2M devices also have dramatically increased on-chip memory capacity to support higher bandwidth, SERDES-based applications. LatticeECP2M Embedded Block RAM capacity ranges from 1.2 Mbits up to 5.3 Mbits, representing up to a 400% increase over competitive low cost architectures. The LatticeECP2/M FPGA families offer a comprehensive array of features that include:
With the addition of 4 to 16 channels of 3.125 Gbps SERDES, the LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low cost SERDES capability for PCI Express and Ethernet based chip-to-chip and small form factor backplane applications.
The LatticeECP2M family includes five devices ranging in density from 20K LUTS to 95K LUTS. The number of 18x18 multipliers in the LatticeECP2M family also has been increased and now ranges from 24 to 168. Each device provides two Delay Locked Loops (DLLs) and eight Phase Locked Loops (PLLs) for timing control. The devices are available in a variety of fine pitch BGA (fpBGA) packages offering 140 to 616 I/O pins and operate from 1.2V power supplies.
LatticeECP2M Block Diagram
The LatticeECP2M family maintains all of the compelling features of the LatticeECP2 family, including DSP functionality, that are required for high-volume, cost sensitive applications. The SERDES integrated into the LatticeECP2M has been engineered specifically for implementation in a cost effective, power efficient (power consumption as low as 100mW) quad-based architecture with 1 to 4 quads, depending on the size of the device. Each quad features 4 SERDES channels (4 complete TX and RX channels) and supports data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry are also built onto the chip. The SERDES/PCS combination is designed to support today's most common packet-based protocols, including:
The combination of SERDES, high performance DSP and a low cost FPGA fabric is extremely attractive to Edge and Access system vendors that are integrating these serial protocols into their wireless base stations, radio network controllers, DSLAMs and other last mile aggregation equipment that enable "triple play" technologies. Mass storage, high-speed server, medical imaging and industrial equipment system designers interested in low cost signal processing also benefit from the LatticeECP2M family's unique combination of features.
Design support for the LatticeECP2M devices is provided by the latest version of Lattice's ispLEVER design tool suite. The ispLEVER design tools provide access, in one software package, to all Lattice digital devices and include synthesis support from Mentor Graphics and Synplicity. As with the LatticeSC FPGA devices, a convenient module-based GUI (graphical user interface) greatly simplifies configuring the SERDES.
Users also have easy access to key ispLeverCORE Intellectual Property modules through the IPexpress design flow. IPexpress-supported functions include:
The LatticeECP2M35 Engineering Samples are available now with production release in the first quarter of 2007. The rest of the family will begin sampling in the first half of 2007.
© Lattice Semiconductor Corporation 2012
