February 2011Electronic systems are becoming increasingly more complex with higher levels of integration of digital and analog circuitry. System optimization for price and functionality often require power supplies to provide many different voltages to support various analog, digital and interface ICs. With system costs increasing, the decision must be made whether to replace or repair returned products. Adding to the replacement cost is the initial attempt of repair adding additional labor cost. A system designed with fault logging can minimize diagnostic time and scrap, reducing overall product cost. Troubleshooting returned products is then reduced to reading the logged fault, replacing a component and testing to verify the correction. By minimizing repair time and scrap a company has a distinct competitive advantage.
Designing for fault logging is a three-fold issue:

Fault Logging Design Block Diagram
The ispPAC-POWR1220AT8 provides an integrated system that allows up to 12 voltages to be monitored. The CPLD architecture allows all control and fault monitoring to be done simultaneously and reported in less than 100usec – several orders of magnitude faster than can be achieved with DSP or a microcontroller.
Faults captured by the POWR1220AT8 are logged to SPI memory with an inexpensive PLD, such as the MachXO. A small hold-up capacitor can be added to the supply output to give ample time to complete the fault logging process. The full solution is demonstrated on the Power Manager II Hercules Development Kit. Fault logging can also be accomplished by using Platform Manager and a SPI memory device. Platform Manager combines the functions of the POWR1220AT8 and the digital management of the MachXO into a single package, greatly reducing the footprint over other solutions.
For further information on fault logging with the Power Manager II or Platform Manager device families, see the following reference designs: