February 2010|
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New Examples Speed the Design-in of Fine-Pitch BGA PackagesA consistent theme voiced by surveys of programmable logic designers is that after timing closure, PCB system-level integration is regarded as the largest challenge they face. Lattice has recently released new design resources that will help PCB and system engineers adopt the fine-pitch ball grid array (BGA) packages of the popular MachXO and ispMACH 4000ZE PLDs. The PCB CAD resources were developed to help speed the adoption of Lattice fine-pitch (0.8 mm or less) ball pitch BGA packages that have emerged as the preferred solution to achieve high I/O density in the smallest system space. A difficulty associated with adopting a BGA-packaged device is how to most efficiently route or “break out” I/O signals from underneath the package to the outside edges. PCB designers must consider the trace width and spacing rules, layer stackup, and via types to ensure the best manufacturing yield at the lowest cost. Having working examples at their fingertips will be very convenient for designers and help speed them through the BGA design-in step, allowing them more time to focus on other design considerations of the PCB. The suite of examples is posted in the PCB Design Support section of the Lattice web site. Technical Note TN1074, PCB Layout Recommendations for BGA Packages, highlights the examples.
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Several PCB layout examples are provided using 0.4 mm to 0.8 mm ball-to-ball center BGA packages. In many cases alternative implementations are provided to illustrate ways to reduce fabrication cost. Each example download includes a PCB layout design in a Mentor Graphics PADS Layout compatible format ASCII (.asc) or PADS Layout (.pcb), NCDrill list, and CAM/Gerber artwork. Each package example is built to comply with IPC7351 specifications and nomenclature conventions. Package breakouts are available for the 64-ball csBGA, 64-ball ucBGA, 100-ball csBGA, 132-ball csBGA, 144-ball csBGA and 256-ball caBGA using a variety of MachXO and ispMACH 4000ZE devices.
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