February 2010

Get to Know the LatticeECP3 FPGA Family

Even though the high-value, low-power LatticeECP3 FPGA family was introduced less than one year ago, these mid-range devices are already in full production and have received broad industry recognition, including “Product of the Year” from Electronic Products magazine.

By making careful design choices and minimizing die size, Lattice offers designers the benefits of high-speed serial I/O and processing capabilities, without the power and cost premiums typically associated with these types of devices. For example, to minimize power consumption the LatticeECP3 FPGA family uses variable channel lengths, optimized low-power transistors and improved routing defaults and algorithms. As a result, the ECP3’s total power consumption has been reduced by over 50% for typical designs, compared to competitive SERDES-capable FPGAs.

The five devices that comprise the low-power ECP3 FPGA family all offer standards-compliant multi-protocol 3G SERDES, the industry’s only DDR3 memory interface for mid-range FPGAs, and high-performance, cascadable DSP slices that are ideal for high-performance RF, baseband and image signal processing. Toggling at 1 Gbps, the ECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O. The entire ECP3 family is manufactured using Fujitsu’s advanced low-power process technology.

The ECP3 FPGA family’s high-performance features include:

• 3.2 Gbps SERDES with 10 GbE XAUI jitter compliance and the ability to mix and match multiple protocols on each SERDES quad. This includes PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and Gigabit Ethernet.
• The SERDES/PCS blocks have been designed specifically to enable the design of the low-latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.
• Compliance to the SMPTE Serial Digital Interface standard, with the unprecedented ability to support 3G, HD and SD video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.
• DSP blocks allowing up to 36x36 Multiply and Accumulate functions running at 500MHz. The DSP slices also feature innovative cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic.
• 800 Mbps DDR3 memory interfaces, with built-in read and write leveling.
• 1 Gbps LVDS I/O, with Input Delay blocks, allows interfacing to high performance ADC and DACs.

With these features, the LatticeECP3 FPGA family is uniquely suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications.

The ECP3 family is supported by a comprehensive ecosystem that includes IP cores (including PCI Express, CPRI and CFR/DPD) and development kits. Vist the Lattice web site for more information about the ECP3 FPGA family, IP cores and development kits.