February 2010

LatticeECP3 DDR3 SDRAM Controller IP Core Released

The industry's only DDR3 memory controller in a low-cost FPGA supports interfacing to both DDR3 devices and DDR3 DIMMs .

Lattice has released a full-featured DDR3 SDRAM Controller IP core. This general-purpose memory controller interfaces with industry-standard DDR3 memory devices/modules compliant with the JESD79-3C DDR3 SDRAM Standard and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to deal directly with the DDR3 memory interface.

 A block diagram of the LatticeECP3 DDR3 SDRAM Controller is shown below.

DDR3 SDRAM Controller IP Core Block Diagram

The DDR3 SDRAM Controller connects to the LatticeECP3 DDR3 memory interface blocks (I/O modules) and clocking circuitry to provide users with an out-of-the-box solution for interfacing to DDR3 memory components and DIMMs. The controller implements a number of features to improve overall throughput. For example, command pipelines are implemented to improve overall throughput. The IP core uses efficient bank management techniques to manage multiple banks in parallel. This minimizes access delays and helps improve the memory bandwidth.

Software Support

The LatticeECP3 DDR3 SDRAM Controller can be generated using the Lattice IPexpress tool. The GUI-based tool allows designers to specify the memory controller parameters (clock rate, data bus width, configuration, etc.) to generate the IP core. Designers can customize the parameters through the GUI. For example, users can control the memory timing parameters and regenerate the SDRAM Controller with fresh timing values. Along with this IP core, simulation models and test benches are provided for users to test their designs before taking them to a board. A demo package allows designers to see the operation of the DDR3 SDRAM Controller using the LatticeECP3 I/O Protocol Board.

To Learn More

For further information on the DDR3 SDRAM Controller IP Core visit the Lattice web site or contact your local Lattice sales representative.