February 2009
A list of recently published documents, including descriptions and ordering numbers.
On-line versions of these publications are available on the Lattice website at www.latticesemi.com. Some documents are also available in print. To order print versions, call your local Lattice representative or Lattice's Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
| Title | Description | Web | Order # | |
|---|---|---|---|---|
| General Information | ||||
| LatticeECP3 Product Brief | Introduction to Lattice's new low power, high-value, SERDES-capable FPGA family. |  |
|
I0198 |
| MachXO Product Brief | Overview of Lattice's low-cost, non-volatile, infinitely-reconfigurable PLD. | |
|
I0176E |
| MachXO Mini Development Kit Product Brief | Introduction to the MachXO Mini Development Kit, an easy-to-use, low-cost platform for evaluating and designing with MachXO PLDs. | |
|
I0199 |
| ispClock5400D Product Brief | Introduction to Lattice's new ultra low jitter in-system programmable differential clock devices. | |
|
I0200 |
| RoHS Compliant Packaging Product Brief | Overview of Lattice's lead-free and halogen-free RoHS-compliant products. | |
— | — |
| Package Selector Card | Features actual size package photos and specification tables for the most popular Lattice device families. | |
|
I0183N |
| ispLEVER Design Tools Brochure | Overview of Lattice's complete design environment for project management, IP integration, design planning, place and route, in-system logic analysis, and more. | |
— | — |
| ispLEVER Software Maintenance Brochure | Explains the benefits of keeping software maintenance active. | |
— | — |
| ispLEVER Upgrade Brochure | Describes the benefits of upgrading from the downloadable ispLEVER-Starter tools to the full ispLEVER software suite. | |
— | — |
| Power Considerations in FPGA Systems: How the LatticeECP3 Stacks Up Against the Competition White Paper | A comparison of the LatticeECP3 FPGA family and competitive devices. | |
— | — |
| High-Speed SERDES Interfaces In High-Value FPGAs White Paper | Discusses the high-speed SERDES interfaces available with the LatticeECP3 FPGA family. | |
— | — |
| Embedded Signal Processing Capabilities of the LatticeECP3 sysDSP Block White Paper | Discusses the embedded signal processing capabilities of the LatticeECP3 FPGA devices. | |
— | — |
| Data Sheets and Handbooks | ||||
| LatticeECP3 Family Data Sheet | Full specifications for Lattice's new low power, high-value, SERDES-capable FPGA family. | |
— | — |
| LatticeECP3 Family Handbook | Complete LatticeECP3 Family Data Sheet plus detailed technical notes on using the key features of this device family. | |
— | — |
| ispClock5400D Family Data Sheet | Full specifications for Lattice's new ultra low jitter in-system programmable differential clock devices. | |
— | — |
| ispClock Family Handbook | Complete data sheets for the ispClock5300S, 5600A and 5400D devices and detailed technical notes on using the key features of this device family. | |
— | — |
| Technical Notes | ||||
| LatticeECP3 SERDES/PCS Usage Guide | Describes the embedded SERDES and associated PCS logic of the LatticeECP3 FPGAs that can be configured to support numerous industry standard high-speed data transfer protocols. | |
— | — |
| LatticeECP3 sysIO Usage Guide | Describes the sysIO standards supported by LatticeECP3 FPGAs and how to implement them using ispLEVER design software. |
|
— | — |
| LatticeECP3 Memory Usage Guide | A guide for integrating the EBR- and PFU-based memories of the LatticeECP3 family in ispLEVER. | |
— | — |
| LatticeECP3 High-Speed I/O Interface | Discusses how to utilize LatticeECP3 devices to implement both the high-speed generic DDR interface and the DDR and DDR2 memory interfaces. | |
— | — |
| LatticeECP3 sysCLOCK PLL/DLL Design and Usage Guide | Describes the clock resources available in the LatticeECP3 device architecture. | |
— | — |
| LatticeECP3 sysDSP Usage Guide | Discusses how to access the features of the LatticeECP3 sysDSP (Digital Signal Processing) slice. Designs targeting the sysDSP slice can offer significant improvement over traditional LUT-based implementations. |
|
— | — |
| LatticeECP3 sysCONFIG Usage Guide | Covers all the configuration options available for the LatticeECP3 FPGA family. | |
— | — |
| LatticeECP3 Soft Error Detect (SED) Usage Guide | Describes the LatticeECP3 family's hardware-based soft error detect (SED) capability. | |
— | — |
| LatticeECP3 Hardware Checklist | Discusses critical hardware configuration requirements and provides a high-level summary checklist to assist in the design process. | |
— | — |
| LatticeECP3 Power Consumption and Management | Discusses power supply considerations for designing with LatticeECP3 FPGAs and guidelines for reducing power consumption. Information on the power calculations provided by the ispLEVER Power Calculator tool. | |
— | — |
| Using a Low-Cost CMOS Oscillator as a Reference Clock for SERDES Applications | This application note shows how to use the ispClock5400D with a low-cost CMOS interface oscillator to provide an ultra-low-jitter clock source for FPGA SERDES applications. | |
— | — |
| Reference Designs | ||||
| BSCAN1 - Multiple Scan Port Addressable Buffer | Multiple Scan Port Addressable Buffer supports hierarchical scan ports to improve test throughput. | |
— | — |
| BSCAN2 - Multiple Scan Port Linker |
Multiple Scan Port Linker offers dynamic links between scan ports in a complex system. |
|
— | — |
| I2C Controller for Serial EEPROMs | I2C master controls serial EEPROM devices through random read cycles. | |
— | — |
| Fast Page Mode DRAM Controller | Provides access to Fast Page Mode DRAM to improve memory access speed. | |
— | — |
| CompactFlash Controller | Supports read and write accesses to/ from a CompactFlash. | |
— | — |
| Read and Write Usercode | Allows users to read or change usercode through the general I/O. | |
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| WISHBONE UART | Provides an interface between the WISHBONE bus and a RS232 serial communication channel. | |
— | — |
| LatticeMico8 to WISHBONE Interface Adapter | Bridges the interoperability of the LatticeMico8 microcontroller and a WISHBONE bus. | |
— | — |
| SPI WISHBONE Controller | Provides an interface between a WISHBONE-complaint microprocessor and external SPI devices. | |
— | — |
| PCI/WISHBONE Bridge | Provides an interface between the PCI initiator and a WISHBONE slave device. | |
— | — |
| I2C Master with WISHBONE Bus Interface | Provides an interface between a WISHBONE-compliant microcontroller and I2C peripheral components. | |
— | — |
| Designing an I2C Master Controller | A fast and highly-flexible I2C master controller to control an I2C bus. | |
— | — |
| Universal Asynchronous Receiver/Transmitter (UART) | A fully-configurable UART implemented in Lattice FPGAs. | |
— | — |
| PCI to NOR Flash Interface | Brings the capability and the performance of the popular PCI Local Bus to the NOR-based Flash. | |
— | — |
| LPC Bus Controller | Provides a Low Pin Count interface for connecting the CPU and its peripherals. | |
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© Lattice Semiconductor Corporation 2012
