February 2009

Letter from the Editors

To Our Readers,

This week is a very exciting one for Lattice. On Monday, February 23 we announced five new products.

First, we are announcing our new LatticeECP3 FPGA family, the lowest-power, highest value SERDES-capable FPGAs in the industry. The LatticeECP3 family inherits and improves upon all the award-winning qualities of our revolutionary LatticeECP2/M FPGAs.

We are also introducing our ispLEVER 7.2 Service Pack 1 design tool suite, which supports the LatticeECP3 and delivers a host of new and expanded features.

For our non-volatile MachXO PLDs we are announcing fifteen new reference designs and a new $59 Mini Development Kit, which are ideal for prototyping high volume, cost sensitive low density applications. We have now shipped over fifteen million MachXO devices since their introduction just 3 years ago, and we expect that momentum to continue as more and more customers are choosing this versatile, easy-to-use PLD family.
 
Also announced today is the new ispClock5400D family of differential clock distribution ICs. The ispClock5400D enables the use of a lower cost, lower frequency CMOS oscillator with SERDES-capable FPGAs such as our LatticeECP3 devices.

To support designs using the ispClock5400D, as well as our other mixed signal Clock and Power Manager devices, we have introduced the new PAC-Designer 5.0 software design tool suite.

While 2009 promises to be a challenging one, be assured that Lattice is aggressively positioning itself for long term success by investing now in a programmable logic product portfolio that will be second to none.

Regards,

The Editors