New Account     Sign In         see this page in Japanese

LatticeNEWS February 2009

Contents

ispLEVER LogoispLEVER Service Pack 1 Available Now 

Update includes new device support, 3rd party tools, new product features and more.

We are pleased to announce the latest upgrade for the Lattice ispLEVER FPGA design software – version 7.2 Service Pack 1 (SP1). This important upgrade includes:

  • Support for the LatticeECP3 FPGA family
  • Improved clock boosting algorithm to improve runtime and performance
  • Updated Power Calculator, SSO Analyzer, and Mico32 tools
  • Reveal hardware debugger support for LatticeECP3 and MachXO products
  • Updated 3rd-party synthesis and simulation tools

A full listing of the new features included with ispLEVER 7.2 SP1 is available here.

LatticeECP3 FPGA Family Support

The ispLEVER 7.2 Service Pack 1 release provides complete implementation and verification support for the LatticeECP3 FPGA family including advanced place and route algorithms to reduce runtime on large designs and a clock boosting flow to increase performance. Designers with applications targeting the LatticeECP3 family for its low power consumption can plan with confidence using Power Calculator, the FPGA industry’s leading tool for power estimation and calculation. Power Calculator measures not only typical power consumption but also worst case power consumption based on actual silicon measurements. “What-if” analysis is virtually effortless as Power Calculator quickly recalculates power consumption under different environmental conditions such as temperature, voltage and activity factors.

The SSO Analyzer enables users to see whether their planned pin layout has enough noise margin to operate reliably. Using the SSO Analyzer, “what-if” analysis of different environmental conditions, such as the noise added by the board’s layout, can estimate results without first building the board, avoiding costly re-spins. In addition, ispLEVER tools such as the LatticeMico32 System used to implement the open source LatticeMico32 soft microprocessor and the Lattice Reveal RTL-based hardware debugger now also support the LatticeECP3 family.

Additional Mach XO Support

The ispLEVER 7.2 Service Pack 1 release adds Lattice Reveal RTL-based hardware debugger support for MachXO1200 and 2280 devices. MachXO designers can include debug access to their designs using the Reveal software with the ability to manage resources by using distributed RAM or EBRs for data capture.

New 3rd Party Tools

ispLEVER 7.2 SP1 features the latest releases of Synopsys Synplify Pro for Lattice v9.6L2 for Windows, Linux and UNIX platforms. This powerful synthesis tool ensures that all designers can get the best possible implementation of their designs in Lattice FPGAs. Also included for Windows users is the Active-HDL Lattice Edition v8.1sp1 simulation environment, including fast and powerful features and tools for FPGA design, verification and debug.

Availability

ispLEVER 7.2 Service Pack 1 is available now for all users of the ispLEVER 7.2 software. It can be downloaded via the ispUPDATE utility included with the ispLEVER 7.2 software, or directly via the Lattice website.