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 New LatticeECP3: Industry’s Lowest-Power, Highest-Value FPGA in Production Today
SERDES-capable LatticeECP3 consumes half the power of competitive devices at half the price.
The LatticeECP3 is the third generation of the high-value LatticeECP (Economy Plus) FPGA architecture, built on an ultra low-power, cost-optimized 65nm process. Like its predecessor, the LatticeECP2M, the LatticeECP3 family once again redefines mid-range, value-based FPGAs. The LatticeECP3 lowers costs and reduces static power consumption by 80%, and total power consumption by 50%, as compared to competitive SERDES-capable FPGAs.
Features
The LatticeECP3 FPGA family is ideally suited for deployment in high volume, cost and power-sensitive applications, including wireless infrastructure, wireline access equipment, video, and imaging. This family offers the following features:
- Logic densities from 17K LUTs to 149K LUTs and up to 586 user I/O.
- Up to 6.8Mbits of embedded memory.
- 3.2Gbps SERDES with XAUI jitter compliance and the ability to mix and match multiple protocols on each SERDES channel. These include PCI Express, CPRI, OBSAI, XAUI, Serial RapidIO and GbE.
- SERDES/PCS blocks designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.
- SMPTE Serial Digital Interface standard compliant, with the unprecedented ability to support 3G, HD and SD/DVB-ASI video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.
- Up to 36x36 Multiply and Accumulate blocks in each slice running at >400 MHz.
- Cascadable DSP slices for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic. Ideal for high performance RF, baseband and image signal processing.
- 800Mbps DDR3 memory interfaces, with built-in read and write leveling.
- 1Gbps LVDS I/O, with input delay blocks, allows interfacing to high-performance ADC and DACs.
 LatticeECP3 Block Diagram
LatticeECP3 Selection Guide
| Device |
ECP3-17 |
ECP3-35 |
ECP3-70 |
ECP3-95 |
ECP3-150 |
| LUTs (K) |
17 |
33 |
67 |
92 |
149 |
| EBR SRAM (Kbits) |
552 |
1327 |
4420 |
4420 |
6850 |
| EBR SRAM Blocks |
30 |
72 |
240 |
240 |
372 |
| Distributed RAM (Kbits) |
36 |
68 |
145 |
188 |
303 |
| 18x18 Multipliers |
24 |
64 |
128 |
128 |
320 |
| 3.2Gbps SERDES Channels |
4 |
4 |
12 |
12 |
16 |
| Maximum Available I/O |
222 |
310 |
490 |
490 |
586 |
| PLLs + DLLs |
4+2 |
4+2 |
10+2 |
10+2 |
10+2 |
| Packages |
SERDES I/O Combinations |
| 256-ball ftBGA (17 x 17 mm) |
4 / 133 |
4 / 133 |
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| 484-ball fpBGA (23 x 23 mm) |
4 / 222 |
4 / 295 |
4 / 295 |
4 / 295 |
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| 672-ball fpBGA (27 x 27 mm) |
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4 / 310 |
8 / 380 |
8 / 380 |
8 / 380 |
| 1156-ball fpBGA (35 x 35 mm) |
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12 / 490 |
12 / 490 |
16 / 586 |
Software Support
The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 7.2 Service Pack 1. The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route, in-system logic analysis and more. The ispLEVER software is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. The ispLEVER design tool suite includes Synopsys’ Synplify Pro synthesis for all operating systems supported and Aldec’s Active-HDL Lattice Edition simulator for Windows.
To Learn More
For further information about the LatticeECP3 FPGA family, visit the Lattice website, or contact your local Lattice sales representative.
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February 2009