February 2008

Low-Cost Serial RapidIO Solution for LatticeECP2M FPGA Family

Partnership with Praesum Communications enables low-cost Serial RapidIO connectivity and performance.

Many high-performance embedded computing systems, especially those designed for digital signal processing (DSP), military/industrial, and communications infrastructure applications, require high speed, point-to-point, communications with low latency and low overhead. Designers for these applications often rely on the Serial RapidIO interface standard as their connectivity solution of choice. Unfortunately, system designers have had to rely on costly traditional ASSP or high-end FPGA solutions in order to implement Serial RapidIO-based systems. Until now, no low-cost FPGA SERDES solutions, which enable RapidIO connectivity, have been available. To fulfill this need, Lattice, in conjunction with new ispLeverCORE partner Praesum Communications, now offers a low-cost Serial RapidIO solution for the LatticeECP2M FPGA FPGA family.

Highly Optimized RapidIO Solution Addresses Key Design Challenges

Many Serial RapidIO-based embedded computing platforms, such as wireless communications infrastructures, face increasing competitive pressures to offer more performance and features while addressing three key challenges:

• Power reduction
• Tight form-factor
• Low cost

Traditional high-end FPGAs enable feature enhancement, but often at a premium for power, space, and cost. ASSPs are limited because new features often are implemented in an external FPGA, thereby increasing power, cost, and board "real estate".

Praesum's 1x Serial RapidIO IP core, compliant to RapidIO revision 1.3 specifications, implements an economical solution in the smallest LatticeECP2M-20 (19K LUTs) device, which is available in a small-scale 17 x17 mm 256 fpBGA package. It also supports the 1.2, 2.5, and 3.125 Gbps data rates in the RapidIO specifications. When combined with outstanding LatticeECP2M device attributes, such as low 100 mW/channel power consumption, secure configuration, and easy field upgrade capability, the Lattice/Praesum solution delivers unprecedented performance and value for Serial RapidIO designs.

A Bridging Platform to Control and Data Plane Interfaces

Depending on the options chosen, such as RapidIO Error Management Extensions, the Praesum core utilizes only 50-70% of the LatticeECP2M-20 LUTs fabric, leaving plenty of logic available for additional value-added design, including built-in hooks for system-specific logical layer and transport layer requirements. In fact, with such small utilization, the LatticeECP2M device with Praesum core enables intriguing bridging solutions to data plane and control plane interfaces, such as CPRI and PCI Express, respectively (which Lattice also offers as IPexpress ispLeverCORE solutions).

Thus, designers who need to drive down the critical design axes of power, size, and cost, need the virtues of ASSPs, and the flexibility of FPGAs, need to look no further than the LatticeECP2M/Praesum solution for their next Serial RapidIO design.

Praesum 1x Serial RapidIO IP Core Block Diagram

Solution Can Scale to Even Higher Performance

The 1x Serial RapidIO solution is Lattice's initial offering for low-cost RapidIO applications. Lattice and Praesum recognize that designers need to scale performance for more demanding applications. Therefore, a 4x IP core optimized for LatticeECP2M will follow to address these needs.

To Learn More

Visit the Lattice website to find out more about the Lattice/Praesum solution. Keep watching this space to learn more!