February 2008Upcoming and recent Lattice webcasts are available live and on demand from the Lattice website and are shown in the table below. These one-hour webcasts are presented by Lattice technical staff and may include software demonstrations and question and answer sessions. To view any of the webcasts, go to the webcasts section of the Lattice website and select your topics of interest.
| Webcast Title | Featured Product | Original Webcast Date | Abstract |
|---|---|---|---|
| Interfacing High Sample Rate ADCs to FPGAs | LatticeECP2/M FPGA Family |
02/27/08 |
The ADS6000 is a family of high sample rate (up to 125 Mega Samples Per Second) Analog-to-digital converters (ADC) from Texas Instruments. These ADCs output their digital data serially at speeds greater than 800 Mbps. An FPGA interfacing with this serial bitstream needs to implement deserializer logic operating at the same clock speed. This seminar discusses timing challenges and design details of a deserializer logic implementation within an FPGA fabric and provides the details of a modified implementation that meets all the timings. |
| Optimizing VHDL Coding for More Efficient FPGA Synthesis | ispLEVER Design Tool Suite |
02/06/08 |
FPGA designers who target low-cost systems are attempting to pack as much logic as possible into FPGA devices and at the same time need the best performance possible. This webcast provides practical advice on how to write VHDL code that will produce the most efficient implementation in FPGA devices. It covers detailed do's and don'ts of synthesis coding styles and illustrates the optimization differences with actual FPGA area and timing results. |
| SMPTE SDI Multi-Rate Solution and Evaluation Platform | LatticeECP2M FPGA Family |
12/13/07 |
This webcast provides an overview of Lattice's low-cost SERDES-based FPGA, the LatticeECP2M, and explains how it can be used to implement an SD/HD-SDI multi-rate solution on a single pin. The use of external components to support this are discussed, along with Lattice's SMPTE demo platform. Planned third-party IP cores are also reviewed. |
| FPGA Design Efficiency with Synthesis for ispLEVER | ispLEVER Design Tool and Synplify Synthesis |
12/04/07 |
Learn how to be more efficient and get better results using Synplify synthesis with ispLEVER implementation tools. Understanding tool options, data flow, and source code constraints can make the RTL-to-implementation loop more efficient. |
© Lattice Semiconductor Corporation 2012
