December 2011

Lattice Introduces Next Generation LatticeECP4 FPGA Family

New LatticeECP4 Family Redefines Low Cost, Low Power FPGAs with High Performance Innovations

On November 28, Lattice announced the launch of our next generation LatticeECP4 FPGA family. The new family redefines the low cost, low power mid-range FPGA market with 6 Gbps SERDES in low cost packages, powerful DSP Blocks and hard IP-based efficient Communication Engines. These innovative devices are ideal for cost- and power-sensitive wireless, wireline, video, industrial and computing markets.

The LatticeECP4 FPGA family builds on the award winning LatticeECP3 FPGA family by bringing premium features to mainstream users while maintaining industry-leading low power and low cost. The FPGAs contain up to 250K logic elements (LUTs), 12.5 Mbits of embedded memory, 1066 Mbps DDR3 memory interfaces and ample clocking resources. The LatticeECP4 devices are ideal for developing mainstream platforms for a variety of applications such as Remote Wireless Radio Heads, Distributed Antenna Systems, Cellular Base-stations, Ethernet Aggregation, Switching, Routing, Industrial Networking, Video Signal Processing, Video Transmission and Data Center Computing.

The four innovative building blocks in the LatticeECP4 FPGAs are:

• 6G CEI-Compliant SERDES/PCS: Up to 16 CEI-Compliant 6 Gbps SERDES/PCS channels in low cost devices. The high dynamic range SERDES/PCS channels can be operated at speeds from 155 Mbps to 6 Gbps. Each SERDES channel consumes less than 175mW of power at 6 Gbps. The built-in pre-emphasis and decision feedback equalization (DFE) circuitry ensure low BER (bit error rate) and high quality eye diagrams.
• MACO Communication Engines: The powerful MACO (Multi-Access Cost Optimized) Communications Engines are hard-wired Intellectual Property (IP) blocks that implement popular communication protocols using only 10% of the silicon resources and power compared to similar implementations in other FPGA fabrics. LatticeECP4 FPGAs can have up to 22 Communications Engines for PCI Express 2.1 x4, 10 Gigabit Ethernet, Tri-speed MAC, and SRIO 2.1.
• Power sysDSP Blocks: The LatticeECP4 family features powerful digital signal processing (sysDSP) blocks with unique innovations that offer 7x the performance of previous generation LatticeECP3 FPGAs. These proprietary innovations enable designers to implement complex, multi-antenna wireless systems (4x4 MIMO at 40 MHz) and high performance video processing algorithms in low cost, low power FPGA platforms.
• GIGA sysIOs with Embedded CDRs: The new devices contain up to 40 embedded clock data recovery (CDR) circuits, which can be combined with the differential I/Os to implement GIGA serial interfaces with speeds up to 1.25 Gbps. In particular, GIGA serial I/Os can be used to implement popular Gigabit Ethernet and SGMII interfaces. The ability to implement Gigabit Ethernet interfaces using general purpose I/Os conserves the 6G SERDES for higher bandwidth interfaces and enables designers to build high port density communication equipment using the low cost LatticeECP4 FPGAs.

Learn More

For more information on the new LatticeECP4 FPGA family, visit the LatticeECP4 web page. A video demonstration of the LatticeECP4 FPGA Family can be viewed here.