December 2010

HiGig™ Protocol Support with Low-Cost LatticeECP3 FPGAs

Lattice has announced the availability of a HiGig/Ethernet MAC IP core based on the award-winning, low-cost LatticeECP3 FPGA family. With this new small footprint IP core, designers can implement low-cost bridging and switching solutions using Broadcom devices. This allows designers to use a wide variety of Broadcom devices with the leading low-cost FPGA in the industry.

Multiple individual devices can be interconnected to operate as one logical network with the HiGig protocol that seamlessly provides features like quality of service (QoS), mirroring and link aggregation. The HiGig MAC ensures that the Media Access rules specified in the 802.3ae IEEE standard and HiGig Protocol definitions are met while transmitting a frame of data over Ethernet. On the receive side, it extracts the different components of a frame and transfers them to higher applications through a FIFO interface.

IP Core

Compliant with Broadcom HiGig and HiGig2™ protocol definitions, the HiGig MAC IP core has a 64-bit wide internal data path operating at a maximum frequency of 156 MHz on the LatticeECP3 FPGA. The core provides XGMII and XAUI interfaces to the PHY layer and supports variable-sized packet transmission with fixed-sized messaging capability (HiGig2 only). With multicast address filtering and 16-bit statistics counters, the core requires approximately 4100 FPGA look-up tables (LUTs) for HiGig implementations and approximately 4700 FPGA LUTs for HiGig2 implementations.

HiGig Ethernet MAC IP Core System Block Diagram

Next Steps

Learn more about the HiGig/Ethernet MAC IP core here or contact your local Lattice sales representative.

HiGig and HiGig2 are trademarks of Broadcom Corporation.