December 2009

Lattice and Praesum Communications Partner to Offer the First Low-Cost FPGA with Serial RapidIO 2.1 Support

The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors). Serial RapidIO enables chip-to-chip, board-to-board, and system-to-system communications and is targeted at the networking, embedded, and storage markets. RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing. In the past, vendors had to rely on expensive, premium FPGAs for these applications.

On November 23, Lattice and Praesum Communications announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family. The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. Lattice also announced that it has licensed this IP core from Praesum and has full rights to use and sub-license the Serial RapidIO IP core.

The combination of the Serial RapidIO 2.1 core and the LatticeECP3 FPGA enables customers to develop low-power infrastructure solutions for 3G, LTE and WiMAX without sacrificing performance or cost. The Serial RapidIO 2.1 core and other Lattice IP cores such as low latency CPRI and GbE/SGMII comprise a comprehensive IP suite in support of wireless infrastructure applications.

About the Serial RapidIO 2.1 IP Core

Praesum Communications is a leader in RapidIO switching, bridging, and endpoint IP. Its small footprint Serial RapidIO 2.1 IP core can be used for processor bridging, control plane interfaces and bridging to legacy interfaces.

Stack Diagram For LatticeECP3 Serial RapidIO 2.1 Support

The core architecture for the Serial RapidIO 2.1 IP core includes the following features:

• Allows for 1x, 2x, 4x lane configurations
• Up to 3.125Gbps
• Implements physical layer, transport layer, maintenance transaction handling and error management extensions
• Provides infrastructure support for external logical layer functions, enabling maximum flexibility
• Provides a choice of logical layer functions that are important for the application
• Provides a choice of how logic layer functions interact with the rest of the system - SOC bus or streaming interfaces
• Supports software implementations of control plane oriented functions such as doorbells and messages
• Backward compatible with the version 1.3 specification

To Learn More

For additional information about the Serial RapidIO 2.1 IP core, please visit the Lattice web site.