December 2009

Quickly Evaluate the ispClock5400D With New Development Board

The new ispClock5400D Evaluation Board provides an easy-to-use, low-cost platform to evaluate the performance characteristics of the ispClock5406D in-system differential clock distribution device. The board provides access to two of the six output banks of the ispClock5406D, reference clock input, feedback input, coaxial or banana jack power sockets, and pin headers for JTAG and I²C ports. The evaluation board package includes a QuickSTART guide, user’s guide, universal power supply, and a Lattice ispDOWNLOAD cable (HW-USBN-2A).

ispClock5400D Evaluation Board

The evaluation board can be used stand-alone to review the performance and in-system programmability of the ispClock5406D device or as a companion board and clock source for LatticeECP3 FPGA evaluation boards:

• LatticeECP3 Serial Protocol Board
• LatticeECP3 Video Protocol Board

Please visit the Lattice web site for more information, demonstrations and documentation on each LatticeECP3 evaluation board.

Demonstration Designs

Three demonstration designs are provided to highlight key applications of the ispClock5406D device.

The first demo is pre-programmed by the factory to demonstrate jitter performance and in-system time and phase skew adjustments via the device’s I²C interface. By using digital test equipment and SMA cables (not included) you can also capture the clock output characteristics.

Other demos are provided that describe the equipment connections and programming required to use the board as a video or SERDES reference clock for the LatticeECP3 Serial and Video Protocol Evaluation Boards. These demos can be easily modified to use other clock distribution and buffering scenarios.

About the ispClock5400D Device Family

The ispClock5406D and ispClock5410D are in-system-programmable differential clock distribution ICs designed for use in high-performance communications and computing applications. The ispClock5400D family features the CleanClock ultra-low phase noise, third generation PLL. The FlexiClock output section supports multiple logic standards and dual skew control features.

The evaluation board features an ispClock5406D device which provides in-system-programmable zero delay universal fan-out buffers for use in clock distribution applications. The on-board ispClock5406D is a 6-output clock distribution IC. Differential ultra low skew outputs are organized with two banks per group. Each bank may be independently configured to support separate I/O standards (LVDS, LVPECL, HSTL, SSTL, HCSL and MLVDS) and output frequency. In addition, each output provides independent programmable control of phase and time skew. All ispClock5400D configuration information is stored on-chip in non-volatile E²CMOS memory.

Pricing and Availability

The ispClock5400D Evaluation Board (PACCLK5406D-S-EVN) is available from the Lattice Online Store for $240.

For more information on the ispClock5400D Evaluation Board, visit the Lattice web site.