December 2009

EDN China Honors LatticeECP3 FPGA Family and ProcessorPM Power Management Device

The LatticeECP3 FPGA family and ProcessorPM power management device have been recognized as “Leading Products” in the highly-regarded EDN China Innovation Awards competition. The LatticeECP3 devices were the only low cost, low power SERDES-capable FPGAs honored by EDN China.

“Our mid-range ECP3 family has defined an entirely new class of FPGAs that delivers low cost and low power without sacrificing performance and features such as SERDES, large memory and high speed I/O,” said Douglas Hunter, Lattice Vice President of Corporate Marketing. “Power has become a major consideration in FPGA design, and it is especially gratifying that the ECP3 devices are the only low power, SERDES-capable FPGAs to receive the 2009 EDN China Innovation award. We are equally pleased to accept the EDN China Innovation award for our ProcessorPM power management device, a lower cost, more accurate, programmable, single chip solution that integrates the reset generation, watchdog timer and voltage supervision functions found in virtually every microprocessor or DSP design.”

The LatticeECP3 family was recognized in the Programmable Logic category, and the ProcessorPM family in the Power Device category. The 2009 EDN China Innovation Product Awards were chosen by technology managers, researchers and an EDN China editor.