December 2009On November 16, Lattice announced that the LatticeECP3-150 FPGA, the highest-density device in its award-winning high-value, low-power LatticeECP3 mid-range FPGA family, was fully qualified and released to volume production.
Features:
With these advanced features, the LatticeECP3-150 FPGA is ideally suited for highly complex and integrated wireless Remote Radio Heads (RRH) such as MIMO-based RF antenna solutions. It also provides Wireline Access developers with unprecedented high-density, low-cost, low-power Ethernet, SONET and PCI Express solutions, with the lowest cost points and power footprints in the FPGA industry.
LatticeECP3 Block Diagram
A range of intellectual property (IP) cores, including Crest Factor Reduction (CFR), Digital Pre-Distortion (DPD), Serial RapidIO 2.1, CPRI, OBSAI, XAUI, SGMII/Gigabit Ethernet, PCI Express and SMPTE Tri-Rate SDI for serial connectivity, FIR Filters, FFT, Reed-Solomon Encoders / Decoders, CORDIC, CIC and NCO for DSP functions and several others for memory interfaces and connectivity, are available from Lattice and its partners to enable designers to develop time-to-market solutions.
The LatticeECP3 FPGA family is supported by the ispLEVER design tool suite, version 8.0. The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, power analysis, place and route, on-chip logic analysis and more.
For more information about the LatticeECP3 FPGA family, visit the Lattice web site or contact your local Lattice sales representative.
© Lattice Semiconductor Corporation 2012
