December 2008

ispClock5300S: Revolutionizing PCB Clock Distribution

In a synchronous digital system, the clock is the most important basic signal. The clock network or the clock tree carries the fastest signal and has the heaviest load in a given system. As a result, the clock tree layout requires special attention to signal integrity, layout, trace impedance and trace length. It is not uncommon for a board to be re-spun just to address the timing issues.

To improve the reliability of PCB clock networks, a variety of clock distribution methods are available. This article compares traditional methods using discrete component ICs versus new programmable devices, such as the ispClock5300S, that can make clock distribution easier and reduce system costs. As an example, a CPU/Microprocessor/DSP board is used to illustrate each scenario.

A clock network has two sections: the clock frequency source section and the clock distribution section. The clock frequency source can be a crystal oscillator or the clock generator of a clock synthesizer. The clock distribution section uses two types of clock distribution buffers: the Fan-Out Buffer (FOB) and the Zero-Delay Buffer (ZDB). The FOB IC outputs multiple copies of the input clock. It uses multiple output buffers on-chip to re-buffer the input clock to drive the output clocks. The FOB introduces a propagation delay from the input to the output clock. A ZDB IC, on the other hand, integrates a PLL along with a Fan-Out Buffer. The PLL is used to cancel the input-to-output propagation delay, and hence the name Zero-Delay Buffer.

There are many types of off-the-shelf, discrete FOB ICs and ZDB ICs available from many vendors that address a given design criteria. Some of the key features that lead to the selection of a FOB or a ZDB IC are:

• Number of outputs
• Type of I/O logic interface, voltage and drive strength
• Timing budget
  - Propagation time delay
  - Output Jitter
  - Output Skew
  - Device-to-device propagation delay difference

Typically, every circuit board requires a unique set of ZDB and/ or FOB ICs to implement its clock network. As a result, a system with multiple cards may require many clock distribution ICs.

Clock Distribution Example: Using Off-the-Shelf FOB and ZDB ICs

The figure below shows a microprocessor board with two clock nets. The first clock net connects the microprocessor to its peripherals and has tight setup/hold requirements. A ZDB IC is applied to mask the worst-case propagation delay from input to output. The second clock net connects the on-board oscillator to other devices. In this case the clock line is buffered with a FOB IC to ensure proper voltage level and drive strength.

The microprocessor-to-peripheral clock network, where the ZDB IC is used, requires that the clock should reach all the peripheral ICs at the same time. While the ZDB will effectively remove the delay effect of the longest clock connection, the shorter connections can induce hold time violations. To compensate equal length clock traces are added to each of the peripheral ICs. The length of the clock trace is determined by the distance between the ZDB IC and the peripheral IC farthest from the ZDB IC. The clock trace to the peripheral ICs closer to the ZDB is folded multiple times (snaking of traces) to layout longer-than-required traces. The distance between the traces on adjacent folds is determined by the clock frequency. However, if the distance between the traces in a fold is reduced too far in order to save circuit board area, the clock signal simply jumps across the folds as an electromagnetic wave instead of traveling through the entire trace length.

Clock distribution using traditional off-the-shelf FOB and ZDB ICs

Each output of the ZDB drives the clock trace through a termination resistor. This is to ensure that its output impedance matches the impedance of the trace. These termination resistors take up board space and raise cost.

The FOB IC is used to distribute the clock sourced from the oscillator. Timing requirements for this network are more relaxed. In this case neither the input-to-output propagation time delay nor the clock edge arrival time to the receiver ICs are important. Also, there is no need to use the same trace length to route the clock from the FOB to the individual ICs. However, the termination resistors are required to match the trace impedance with the output impedance of the FOB driver.

In some applications, the clock must be distributed using different logic interfaces (CMOS3.3V, CMOS1.8V). In such cases, the design may require the use of two FOB/ZDB ICs to distribute the same clock. The device selection becomes stringent if the design has to ensure that the clock edges reach the receiver ICs at the same time.

Using ZDB and FOB ICs can help improve clock circuit performance and connect a variety of signal standards; however, they do raise overall system cost with additional components, assembly and board space. Another hidden cost is the limited testability of ZDB and FOB ICs.

Commonly, PC board testing during manufacturing uses the JTAG 1149.1 boundary scan standard. The extent of test coverage depends on the number of ICs on the board supporting the boundary scan feature. Most discrete clock ICs do not support the JTAG interface. As a result, designers have to make provisions for indirect boundary scan methods such as using a PLD, or route unused pins of an ASIC or CPU through the clock network during the boundary scan test.

Disadvantages of Using Discrete ZDB and FOB ICs

The disadvantages of using traditional off-the-shelf discrete FOB / ZDB ICs are:

• Almost every board in a system requires a unique set of clock distribution ICs, thereby increasing the Bill of Materials. This increases the cost of carrying and managing the inventory.
• A larger circuit board area is required to accommodate the snaking of traces and external termination resistors.
• A board re-spin may be needed to compensate for deviation of setup and hold times of an IC from its designed value, or due to the improper snaking of traces.
• Board complexity is increased in order to support boundary scan through discrete ZDB/ FOB ICs.
• It is more difficult to achieve timing closure when a clock network requires multiple logic interfaces (due to the cascading of clock ICs/ using two ICs to distribute the same clock).

Programmable Clock ICs

Recent innovations in programmable clock ICs integrate ZDB, FOB and JTAG testability features to create a more flexible solution that reduces overall system cost. The ispClock5300S programmable clock IC from Lattice does not suffer from the discrete drawbacks listed above.

ispClock5300S Architecture

The ispClock5300S effectively integrates up to 20 output ZDB/ FOB ICs and can distribute clocks using a programmable output that can be configured for logic type, termination, slew rate and skew. Any clock output of the ispClock5300S device can be configured as a Zero-Delay Buffer output or a Fan Out Buffer output. A JTAG interface provides in-system programming to meet the requirements of a given application, and boundary scan functions.

There are five members in the ispClock5300S family: 4, 8, 12, 16 and 20 output devices. All five members have the same architecture and specifications. The only difference among them is the number of outputs.

The figure below shows the block diagram of the ispClock5300S device. All clock outputs are shown on the right side of the figure. The programmable termination on each output can be set to match the impedance of the trace without using external resistors. The output section of the ispClock5300S is called the universal fan-out buffer because each of the output logic types can be configured as LVCMOS (3.3, 2.5, 1.8V), LVTTL, SSTL or HSTL. The clock source for each output can be from an internal PLL or a reference clock input and is controlled by the switch matrix. When the clock source is from the PLL, that output clock can be delayed using the corresponding skew control block. The output switch matrix provides multiple paths of interconnection between the outputs and the inputs. As can be seen, any output can be connected to any one of the following:

• Clock output from one of the dividers from PLL providing Zero-delay clock output
• Directly connect to reference input (even though the same clock is connected to the PLL)
• Directly connect to the reference input that is not connected to the PLL

ispClock5300S architecture

The ispClock5300S devices use three 5-bit on-chip output counters to support the generation of up to three clocking frequencies derived from one reference. The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 100ps, regardless of bank and frequency. The maximum cycle-cycle (peak-peak) output jitter is less than 70 ps and the period jitter is less than 12 ps (rms). The output skew of each clock net relative to the reference input can be controlled in delay increments of 156 ps (lead or lag) to minimize the need for the snaking of traces. Both the reference input and the Universal Fan-out Buffers also support a wide variety of popular single-ended logic standards (LVCMOS, LVTTL, HSTL, SSTL) at a variety of voltage levels. The reference input also supports differential clock input logic standards. The input termination and output impedance of each output can be tuned individually to match respective trace impedances, resulting in clock nets with high signal integrity.

Clock Distribution Example: Using ispClock5300S

The figure below shows the single-chip ispClock5300S device performing the functions of ZDB and FOB ICs (as shown in the first figure above). In addition, no external termination resistors are required because they are already integrated into the ispClock5300S device.
 

Clock distribution using ispClock5300S device

In the first figure, the clock traces originating from the ZDB IC required snaking, which wasted circuit board area. However, the clock traces from the ispClock5300S device do not require snaking because the clocks to the nearer peripheral ICs were delayed using the programmable skew feature. The programmable skew feature also can be changed in-system, using its JTAG port, to compensate for changes in the setup and hold times of individual peripheral ICs.

The JTAG interface port can be used to program the ispClock5300S IC as well as the boundary scan function, reducing manufacturing time.

Advantages of Using ispClock5300S for Clock Distribution

The advantages of using ispClock5300S for clock distribution are:

• The ispClock5300S can be used across a wide verity of circuit boards because it can be programmed to meet board-specific clock distribution requirements
• Requires the smallest circuit board area because the need for snaking traces is minimized and no external termination resistors are required
• Board re-spins can be avoided by compensating for the deviation in the setup and hold times of peripheral ICs through the programmable skew feature
• Because the ispClock5300S device supports the JTAG boundary scan feature it does not require indirect methods to aid board testing during manufacturing
• It is easy to achieve timing closure with ispClock5300S because there is no need for cascading multiple clock distribution ICs to support different logic interfaces. Each output of the ispClock5300S can be programmed to meet the required logic interface. 

Programmable Clock ICs Help Standardize PCB Clock Solutions

A programmable clock IC provides system engineers a way to standardize a PCB clock solution across products. By integrating ZDB, FOB and JTAG functions, along with a variety of signal driver buffers, the ispClock5300S minimizes PCB redesigns and cost.

To Learn More

For further information about the ispClock5300S device, visit the Lattice website or contact your local Lattice sales representative.