December 2007

New Throughput Demo Measures PCI Express Performance

Demo Enables Measurement of High-Throughput PCI Express Applications with LatticeECP2M and LatticeSCM Devices

Designers of many PCI Express endpoint applications, typically PC add-in cards, often require the test and measurement of system performance in order to ensure that the endpoint meets with requirements. Throughput operations from the endpoint directly to and from system memory are particularly critical to measure. The new Lattice PCI Express Throughput Demo has been created to demonstrate how maximum throughput may be measured using the built-in Stored FIFO Interface (SFIF) logic of the Lattice PCI Express core.

The demo can be found here: PCI Express x1 and x4 MACO Core.

Utility of the Demo

Figure 1 is a block diagram of the PCI Express Throughput Demo. The demo includes a TLP (Transaction Layer Packet) generator added to the PCI Express IP core transaction layer which interfaces to the system through the SFIF. The demo measures and displays the core’s throughput to and from the root complex of the PC. This includes measurement of the data rates of write transactions from the add-in card to the PC and read transactions from the add-in card sent to the PC (see Figure 2).

Figure 1. PCI Express Throughput Demo

Figure 2. PCI Express Throughput Measurement GUI

In all cases, the data transfers are initiated by the LatticeECP2M or LatticeSCM evaluation board. With this demo, PCI Express system designers can observe and/or compute the throughput of their endpoint with the intended end system. It should be noted that while this is a general-purpose throughput demo, the type of system, the types of PCI Express slots available in the system, as well as the load on system memory will affect the measured results.

Future Demo Applications

In the PCI Express market, system vendors have typically created their own schemes for increasing performance. Keeping this in mind, the Lattice PCI Express core has been designed as a flexible IP core which enables a high degree of customization for designers to either implement their own performance schemes or adopt those provided by Lattice.

Lattice recognizes the need for increasing PCI Express performance and has created a roadmap to address user needs. The first step in this roadmap is the Throughput Demo, which will be followed by demos using simple DMA (Direct Memory Access) for local system memory, and scatter-gather type of DMA for non-contiguous memory.

To Learn More

Further information about the Throughput Demo can be found in the Lattice PCI Express Throughput Demo User's Guide PDF.

The demo can be found here: PCI Express x1 and x4 MACO Core.