December 2007A list of recently published documents, including descriptions and ordering numbers.
On-line versions of these publications are available on the Lattice website at www.latticesemi.com. Some documents are also available in print. To order print versions, call your local Lattice representative or Lattice's Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
| Title | Description | Web | Order # | ||
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| General Information | |||||
| Package Diagrams | Updated to include 1152 fpBGA package diagram. |  |
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| ispClock Product Brief | Introduction to the ispClock integrated univeral fan-out buffer offering programmable skew and output impedance control. | |
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I0168E | |
| User's Guides | |||||
| Lattice PCI Express Throughput Demo User's Guide | How to install and run the Lattice PCI Express Throughput Demo on a Windows system (Microsoft Windows2000, Windows XP SP2, Server2003). |
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| PCI Express Demo for Linux 2.4 User's Guide | How to install and run the Lattice PCI Express Endpoint IP Demo on a Linux system. |
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| FIR Filter IP Core v.3.0 User's Guide | How to use the Lattice FIR (Finite Impulse Response) Filter IP core, a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP blocks available in Lattice devices. |
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| Application Notes | |||||
| Interfacing the Trim Output of Power Manager II Devices to DC-DC Converters | An overview of the trim/margin capabilities of the ispPAC-POWR6AT6 and ispPAC-POWR1220AT8 devices and detailed instructions on how to use PAC-Designer software to incorporate almost any adjustable DC-DC converter into a trimmed and margined power supply system. |
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| Stable Operation of DC-DC Converters with Power Manager Closed Loop Trim | Explains why adding Power Manager Closed Loop Trim to a DC-DC converter does not adversely affect the stability of the converter while improving the accuracy of the converter's output voltage. Bode plot analysis shows that system performance with and without closed loop trim has essentially the same transfer function and thus the same phase margin, gain margin, and transient response. |
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| Optimizing the Accuracy of ispPAC Power Manager Timers | Describes in detail the architecture of the Power Manager Timer Circuits so designers can select the optimum settings for the best time-out accuracy. It also explains the sources of timing error so that their influence can be minimized in Power Management applications. |
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© Lattice Semiconductor Corporation 2012
