August 2011

Lattice Diamond 1.3 Design Software for More Robust, Low-Power FPGA Designs

Lattice Diamond design software incorporates an intuitive, modern GUI that employs several innovative concepts. This helps users quickly explore design alternatives to meet their cost, power and performance goals. Version 1.3 provides many new features described below.

More Robust Design and Optimized Cost In Less Time

With Diamond 1.3, users can:

• Design with confidence and ensure designs are more robust and resilient to their operating environment.
• Add user-defined clock jitter to a design’s clocks while performing static timing analysis of the design. Designers can control the amount of clock jitter they want to model through new timing preferences and see the analysis results in both the Trace Report and the Timing Analysis View.  
   

   

  

   

  When using MachXO2 devices or higher-performance LatticeECP3 devices, users are shown pin migration information in the Package View and Spreadsheet View, such as incompatible pins, to help with migrating designs to a lower-cost device while preserving the current package and board layout. This pin migration information can also be exported to the Pin Layout file.

   

   

  

   

  More Efficient Design Flow

  • Projects now support complex multi-file test benches and allow multiple design representations for the same design block (such as one description for synthesis and another for simulation). 
  • The simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator. 
  • The synthesis design constraints flow is now more intuitive and allows for multiple files (.sdc or .ldc) that can be managed similar to the back-end preference files (.lpf).
  • The programmer files (.xcf) are now in the File List as users can program their Lattice devices directly from the Lattice Diamond user interface. 

   

  

   

  • The Reveal Analyzer, Lattice Diamond's on-chip debugger, now works 10x faster when downloading large amounts of trace data, or configuring complex trigger setups.

  Design Exploration Made Easy

  Lattice Diamond 1.3 provides device resource utilization for each logical level of the design hierarchy following synthesis. This enables users to make early design decisions about how to structure their design in order to optimize utilization of the overall device. 

   

  

   

  When exploring design alternatives, designers can use Run Manager to process multiple implementations in parallel. Users can now control which one of the multi-par runs is used so that the rest of the design flow can be focused on the implementation that provides the best placement and routing run for the design.

   

  

   

  Improved Ease of Use

  With Lattice Diamond 1.3, users can now program their devices in a very intuitive fashion. The new Diamond Programmer fully supports the direct programming features of the ispVM System, a comprehensive stand-alone device programming manager. Diamond Programmer significantly improves the ease-of-use of the most common steps such as setting up the cable, scanning the board, and direct programming of the device. Diamond Programmer is available either fully integrated into the Lattice Diamond environment or as a stand-alone tool.

   

  

   

  Enhanced Support for the MachXO2 Device Family

  The Lattice Diamond design environment enables users to easily explore design alternatives as they target cost-sensitive, low-power, high-volume applications – the type of applications ideally suited for the MachXO2 family. Lattice Diamond 1.3 offers:

  • Updated timing and power analysis device information, as well as final production package, bitstream and SSO analysis data based on the actual device characterization for MachXO2 LCMXO2-1200 and LCMXO2-1200U devices
  • Support for a wafer-level package for the LCMXO2-2000U, needed for very high-volume, cost-sensitive applications
  • Fmax improvement of 5% to 15% on most designs targeted to MachXO2 devices

  Integration with PAC-Designer 6.1 Software

  Lattice Diamond 1.3 provides an automated simulation environment not previously available to mixed signal designers, and integrates with PAC-Designer 6.1 software to simplify platform management design. 

  Third-Party Tool Support

  Lattice Diamond software incorporates the OEM versions of:

  • Synopsys Synplify Pro advanced FPGA synthesis for Windows and Linux
  • Aldec Active-HDL Lattice Edition II simulator for Windows

  Lattice devices are also included in the full versions of Synplify Pro and Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.

  Availability and Licensing

  Lattice Diamond 1.3 is available now for download from the Lattice website for both Windows and Linux. Once downloaded and installed, the software can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license.

  The free license can be immediately generated upon request from the Lattice website and provides no-cost access to many popular Lattice devices such as the MachXO2 and MachXO CPLD families and the LatticeECP2/M and LatticeXP2 FPGA families. The Lattice Diamond free license enables Synopsys Synplify Pro for Lattice synthesis as well as the Aldec Active-HDL for Lattice Edition II mixed language simulator.

  Purchase of the subscription license enables all the features of the free license and adds support for all Lattice FPGAs, including the LatticeECP3 devices. The subscription license price is $895 per year.