August 2010XAUI (10-Gigabit Attachment Unit Interface) is a high-speed interconnect that offers a reduced pin count that simplifies the routing of high-speed electrical connections. It delivers 10 Gbps of data throughput by using four differential signal pairs in each direction. Its compact nature and robust performance makes it ideal for chip-to-chip, board-to-board, and chip-to-optics module applications.
The XAUI IP Core for LatticeECP3 FPGAs provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface (XGMII) devices. It implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that, together with PCS and SERDES functions implemented in the FGPA, provides a complete XAUI-to-XGMII solution.
XAUI IP Core Solution - Simplified Block Diagram
The BCM56800 network switch from Broadcom Corporation is a high density, 10-Gigabit Ethernet switching chip solution with 20 ports. Its high level of integration and low power consumption enable system vendors to build high-performance, high-port-density 10-Gigabit Ethernet switches in the same form factor as existing Gigabit Ethernet solutions. Some key features include:
• Based on StrataXGS field-proven, robust architecture
• 20 10GbE/1GbE ports supports 10-Gigabit Ethernet or 1-Gigabit Ethernet
• Integrated high performance XAUI SERDES for all 20 10GbE ports; uses single SERDES lane per port at Gigabit Ethernet speeds
A Physical/MAC layer 10GbE interoperability test was done between a LatticeECP3-150 device on the LatticeECP3 Serial Protocol Board and the Broadcom BCM56800 network switch using a CX-4 to SMA conversion board, to exercise the Physical/MAC layer of the 10GbE protocol stack on the LatticeECP3 device.
LatticeECP3 Interoperability Setup with Broadcom BCM56800
The Broadcom switch transmitted continuous Ethernet frames to the LatticeECP3 device which looped the data at its MAC client interface back to the Broadcom switch. The test between the two device ports ran error free and the Tx, Rx packet counters recorded an identical number of frames for both devices. The LatticeECP3 family therefore offers a 10-Gigabit Ethernet Physical/MAC layer solution that is fully interoperable with the Broadcom BCM56800 network switch.
Download the XAUI Interoperability Report for Broadcom.
The 88X2040 quad transceiver from Marvell Semiconductor is a fully integrated serialization/de-serialization device that incorporates four independent lanes, delivering high-speed bi-directional point-to-point baseband data transmission that supports cost-effective IEEE 802.3ae compliant 10-Gigabit Ethernet and 10-Gigabit Fibre Channel applications. Some key features include:
• Supports a wide range of serial data rates from 1.0 Gbps to 3.1875 Gbps
• Supports 32-bit bi-directional XGMII with 8b/10b ENDEC option, and XAUI
• Performs the parallel-to-serial, serial-to-parallel conversion with integrated Time Base Generator (TBG) and Clock/Data Recovery Circuit (CDRC)
A Physical/MAC layer 10-Gigabit Ethernet interoperability test was done between a LatticeECP3-150 device on the LatticeECP3 Serial Protocol Board and the Marvell 88X2040 device on the Marvell 88X2040 SMA to XGMII Evaluation Board, to exercise the Physical/MAC layer of the 10-Gigabit Ethernet protocol stack on the LatticeECP3 device.
LatticeECP3 Interoperability Setup with Marvell Alaska 88X2040
The Marvell device transmits CJPAT data to the LatticeECP3 device. The LatticeECP3 device loops the data at its MAC client interface back to the Marvell device. The test ran for an hour and the number of frames transmitted by the Marvell device was the same as the number received and retransmitted by the LatticeECP3 MAC client. Additionally, the CRC-error frame generated from the Marvell GUI was recorded and the same frame was looped back in the TX direction of the LatticeECP3 MAC, resulting in an expected TX CRC error count as well. The LatticeECP3 family therefore offers a 10-Gigabit Ethernet Physical/MAC layer solution that is fully interoperable with the Marvell Alaska 88X2040 quad transceiver.
Download the XAUI Interoperability Report for Marvell.
To help users evaluate the XAUI functionality, Lattice has created a LatticeECP3 XAUI Demo that demonstrates the performance of the LatticeECP3 PCS in XAUI mode at 3.125 Gbps. The XAUI Demo Design is a quad-based XAUI generator/checker that transmits/checks XGMII data to/from a PCS quad. In turn, the PCS quad serializes the data in the transmit direction, and de-serializes it in the receive direction. In this demo, the encoded serial data stream is looped back externally via cables using the on-board SMA connectors. In this case, a backplane of variable length can be included in the serial path, or the quad outputs can be connected to its inputs.
For a list of other Ethernet Interoperability visit the Ethernet Solutions page of the Lattice web site.
© Lattice Semiconductor Corporation 2012
