August 2008

Lattice FPGAs with Verilog Training Class Now Available Via the Web

Dates: 2 Classes - September 8-18 or October 20-31, 2008
Cost: $895 if you register by September 1 or October 13 ($1195 for late registrations)
Skill Level: Basic to intermediate

• September Course (16 hours total) 
  - 9/8 to 9/11 (Monday to Thursday) 9:00 - 11:00 am Pacific Standard Time 
  - 9/15 to 9/18 (Monday to Thursday) 9:00 - 11:00 am Pacific Standard Time
• October Course (18 hours total) 
  - 10/20, 10/22, 10/24 (M, W, F) 9:00 - 10:30 am PST & 11:00 am - 12:30 pm Pacific Standard Time
  - 10/27, 10/29, 10/31 (M, W, F) 9:00 - 10:30 am PST & 11:00 am - 12:30 pm Pacific Standard Time

Class Format

Do you want to reduce the design time for your next Lattice FPGA but can’t get away from the office for a week of training? Now you can get up to speed quickly at your location with only 2-3 hours of instruction per day and complete the labs when it’s convenient for you! We use web conferencing to provide interactivity as you share the instructor’s desktop and ask questions via a conference call. The instructor will answer your questions while you work through the labs via email. A course manual binder will be shipped to you upon registration.

Class Content

Learn how to  apply the power of the Verilog language in the Lattice design flow. Make the transition from basic digital design concepts to Verilog constructs. Numerous examples will cover various modeling styles for synthesis and verification, enhancing performance and fine tuning  the FPGA. This comprehensive course is appropriate for beginner to  intermediate designers and covers the following topics:

• Verilog Design Flow with ispLEVER
  - How HDLs work
  - Simulation and synthesis tools
  - Lattice FPGA implementation tools
  - FPGA flow, Verilog code to bit file
• Elements of Verilog Syntax
  - Literal bit vectors
  - Data types: variables vs. nets
  - Assignments and expressions
  - Parameters: symbolic names
• Verilog Operators
  - Concatenate and replicate
  - Bitwise operators
  - Arithmetic operators
  - Shift and rotate operations 
• Dataflow Coding
  - Anatomy of continuous assign
  - Describing glue logic
  - More complex dataflow code
• Structural Verilog Coding 
  - Instantiating sub-modules
  - Using Lattice IPexpress
  - Data types for declaring ports
• Writing and Running Testbenches
  - Instantiate a design under verification
  - Effective stimulus generation code
  - Monitoring response via waveforms 
• RTL Coding for Combinational Logic
  - Algorithmic description of hardware
  - Anatomy of an always construct
  - Nuances of if-else, case(z), for, while
• RTL Coding for Sequential Logic
  - Edge triggered code
  - Non-blocking syntax
  - Resets (asynchronous vs. synchronous)
• Enhancing Performance
  - Using I/O FFs
  - Coding for speed
  - Controlling fanout
• Fine Tuning FPGA Device
  - I/O placement
  - Hold time constraints
  - Floorplanning groups
  - Timing closure strategies

To Learn More

For more information or to register for this course, contact:

Tom Wille
TM Associates, Inc.
503-656-4457
tw@tm-associates.com

Special Offer

Those who attend the TM Associates "Lattice FPGAs with Verilog Training Class" in September or October, 2008 are eligible to receive $300 off the list price of any single purchase of a Lattice evaluation board or software development package. Must be redeemed by December 31, 2008.