August 2008Upcoming and recent Lattice webcasts are available live and on demand from the Lattice website and are shown in the table below. These one-hour webcasts are presented by Lattice technical staff and may include software demonstrations and question and answer sessions. To view any of the webcasts, go to the webcasts section of the Lattice website and select your topics of interest.
| Webcast Title | Featured Product | Original Webcast Date | Abstract |
|---|---|---|---|
| Quick Timing Closure - Simulation & Debug of FPGA Designs | ispLEVER Design Software and Lattice FPGAs |
9/15/08 |
Some designers skip timing simulation, not realizing that it can complement static timing analysis (STA) tools and help achieve timing closure faster. Don’t make the same mistake, identify and address problems earlier using a simulator and STA tools in concert. This Webinar will use a Lattice reference design throughout, to show you how to use STA results to prepare a test bench, extract timing models from FPGA design tools, understand simulation results, and identify/trace problems before you program your Lattice FPGA. To wrap-up the verification process, designers can compare timing results against functional results to ensure design integrity. |
| Evaluating and Enhancing PCI Express Performance |
Lattice PCI Express IP Cores, Evaluation Boards and Demos |
8/13/08 |
This webcast presents Lattice's PCI Express IP offerings, various hardware evaluation platforms, and the associated demos and reference designs for evaluating PCI Express. With PCI Express IP and the Lattice SG-DMA IP Core, Lattice offers a complete portfolio of demos that help designers evaluate the throughput through the PCI Express link and demonstrate a complete PCI Express system solution. These solutions offer designers an excellent starting point for their own PCI Express designs and allow them to make system-level architectural decisions even before they start their own designs. |
| Wireless Solutions with Lattice FPGAs | LatticeECP2 FPGA Family | 8/06/08 |
Going forward, the movement is on from 3G to 4G. New, competing approaches such as WiMAX and LTE have arrived and base station topologies are evolving as well. Traditional implementations that co-locate the base station with the power amplifier and antenna are being replaced by distributed topologies where there is a central base station serving multiple remote antennas called Remote Radio Heads (RRH). This supports a smaller overall footprint and an overall lower cost for providers that facilitates the more rapid development of cellular networks. Lattice offers an array of solutions to address this ever-changing market, starting with the Lattice ECP2M family. This unique family of devices offers designers the best of both worlds...a low cost FPGA fabric combined with the performance of integrated SERDES and DSP technology. This family serves as the ideal platform for various solutions including CPRI and OBSAI, high speed data conversion as well as RF and Baseband processing. |
| Low-Power Design with CPLDs | ispMACH 4000ZE CPLD Family |
-- |
This EduCast introduces the ispMACH 4000ZE CPLD which brings the benefits of programmable logic to designers of low-power electronic systems. A detailed description of the new, low-power features of this product are presented. The ispMACH 4000ZE is based on the popular ispMACH 4000 architecture, a reliable mainstay in the CPLD industry for general purpose logic applications. |
| Mitigating Microprocessor Obsolescence with FPGAs |
Lattice FPGA Families |
6/25/08 |
Microprocessor and microcontroller End-of-Life announcements signal a potentially costly problem for those who design long life-cycle products. This webcast will focus on ways to use reprogrammable FPGAs to avoid the potential trauma of these announcements. Attend this webcast to see how two designers used Lattice FPGAs to save their designs with little or no impact to their existing hardware and software. |
© Lattice Semiconductor Corporation 2012
