August 2007A list of recently published documents, including descriptions and ordering numbers.
On-line versions of these publications are available on the Lattice website at www.latticesemi.com. Some documents are also available in print. To order print versions, call your local Lattice representative or Lattice's Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
| Title | Description | Web | Order # | |
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| General Information | ||||
| LatticeSC FPGA Family Product Brief | Introduction to the LatticeSC Extreme Performance programmable System Chip FPGA family. |  |
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I0181D |
| Designing Power Manager II with PAC-Designer Tutorial | This tutorial shows you how to use several processes, tools, and reports of the PAC-Designer software suite to program the POWR1220AT8 device. Learn how to meet the sequencing and management needs of a simple circuit board with a variety of voltage rails and ICs. | |
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| ispClock5312S Evaluation Board User's Guide | Guidelines for operation of the ispClock5312S Evaluation Board. | |
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| LatticeXP2 Advanced Evaluation Board User's Guide | Guidelines for operation of the LatticeXP2 Advanced Evaluation Board. | |
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| LatticeSC PCI Express x4 Evaluation Board User Manual | Guidelines for operation of the LatticeSC PCI Express x4 Evaluation Board. | |
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| Data Sheets and Handbooks | ||||
| LatticeECP2/M Family Data Sheet | Full specifications for Lattice's low cost, high performance FPGA family. |
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| LatticeECP2/M Family Handbook | Complete LatticeECP2/M Family Data Sheet plus detailed technical notes on using the key features of this FPGA family. |
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| LatticeSC/M Family Data Sheet | Full specifications for the LatticeSC/M (System Chip) family of FPGAs. | |
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| LatticeSC/M flexiPCS Data Sheet | Full specifications for the embedded multiprotocol Physical Coding Sublayer in the LatticeSC/M FPGA family. | |
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| Technical Notes | ||||
| LatticeECP2/M Hardware Checklist | Describes critical hardware configuration requirements for designing complex hardware using the LatticeECP2/M FPGA. Covers power supplies, configuration mode selection, device I/O interface and critical signals. | |
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| LatticeECP2M/Marvell Gigabit Ethernet Physical Layer Interoperability |
Describes a 1000BASE-X physical layer Gigabit Ethernet interoperability test between a LatticeECP2M device and the Marvell Alaska Ultra 88E1111/88E1112 devices. |
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| Intellectual Property | ||||
| Scatter-Gather Direct Memory Access Controller IP Core User Guide |
Detailed user's guides for Lattice's latest IP core products. |
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| XAUI 10Gb Ethernet Attachment Unit Interface IP Core User Guide | |
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| FIR Filter Generator IP Core User Guide | |
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| Color Space Converter IP Core User Guide | |
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| Block Convolutional Encoder IP Core User Guide | |
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| Correlator IP Core IP Core User Guide |
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| Turbo Encoder IP Core User Guide |
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| Turbo Decoder IP Core User Guide |
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| Distributed Arithmetic FIR (DA-FIR) IP Core User Guide |
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© Lattice Semiconductor Corporation 2012
