August 2007

Lattice Listens

Question:

What are some of the hardware design guidelines I should be aware of when designing with the LatticeECP2/M, LatticeXP2 and LatticeSC FPGA families?   

Answer:

The 90nm generation of the Lattice FPGA families mentioned above can support high-speed interfaces such as generic source synchronous LVDS from 750Mbps to 2Gbps, DDR2 memory interfaces from 400Mbps to 533Mbps and SERDES interfaces supporting speeds from 270Mbps to 3.125Gbps. Guidelines relating to high-speed interfaces, power supplies and FPGA configuration design recommendations are provided for system designers. The following is a list of documentation relating to these areas that will help you get started. 

High-Speed Interface Technical Notes:

• TN1114 - TN1114 – Electrical Recommendations for Lattice SERDES
• TN1033 – High-speed PCB Design Considerations

Power Supply and FPGA Configuration Technical Notes for LatticeSC FPGAs: 

• TN1101 - Power Estimation and Management for LatticeSC Devices
• TN1080 – LatticeSC sysCONFIG Usage Guide

Power Supply and FPGA Configuration Technical Notes for LatticeECP2/M FPGAs:

• TN1106 – Power Estimation and Management for LatticeECP2/M Devices
• TN1108 – LatticeECP2/M sysCONFIG Usage Guide
• TN1162 – LatticeECP2/M Hardware Checklist

Power Supply and FPGA Configuration Technical Notes for LatticeXP2 FPGAs:

• TN1139 – Power Estimation and Management for LatticeXP2 Devices
• TN1142 – LatticeXP2 sysCONFIG Usage Guide
• TN1143 – LatticeXP2 Hardware Checklist

These technical notes are based on real hardware implementations and provide helpful information to guide you through your high-speed design using these FPGA device families.