August 2007The new ispClock5312S Evaluation Board provides a convenient platform for evaluating the ispClock5312S device, or helping to develop and program your own design. SMA I/Os and carefully matched 50-ohms microstrip transmission lines give you clean access directly to the ispClock5312S device, allowing you to see how the ispClock5312S will perform in any condition or mode you need.
The ispClock5312S device is a versatile in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. Whether you need a zero-delay buffer, a non-zero-delay buffer, or some combination solution, you can easily program the ispClock5312S to fit your needs. The ispClock5312S operates from 8MHz to 267MHz with a low (<100ps) output-to-output skew, and low jitter (<70ps peak-to-peak). The in-system programmability of the ispClock5312S makes it an especially versatile solution. Output buffers can be programmed to a number of single-ended output standards, impedance, and slew rates. The high-performance on-chip PLL, programmable output skew (per output), output dividers, and numerous other features make the ispClock5312S a valuable addition to many PCB solutions.
ispClock5312S Evaluation Board
A number of features are provided to help you get running quickly, and easily change configuration modes as you go. These include:
This evaluation board is also 100% lead-free and RoHS compliant.
The ispClock5312S board and the associated schematic design can provide a convenient reference point when developing your own solution. Be sure to check the Lattice website for more resources and information about this and other Lattice evaluation boards. Additional reference resources (such as schematic/layout source files) are available by request from your local Lattice sales office and the ispClock5312S Evaluation Board User's Guide is available on the Lattice website.
© Lattice Semiconductor Corporation 2012
