The LatticeSC/M FPGA families now support HyperTransport technology at rates up to 1600Mbps, QDRII+ rates up to 750Mbps, RLDRAM II rates of 800Mbps and DDR2 interface speeds of 667Mbps. HyperTransport technology and memory interfaces are implemented using the LatticeSC/M families' innovative PURESPEED I/O technology. Full story...
The use of twisted pair cabling for backbone and intra-platform interfaces is becoming increasingly common. Relatively inexpensive and ubiquitous cabling and cable connectors are available that comply with the TIA/EIA-568-A Commercial Building Wiring Standard. Full story...
The number of power supply sources used on today’s circuit boards continues to increase, even as power supply management algorithms become more complex. Now designers can standardize on the ispPAC-POWR1014 programmable, mixed signal power management device across a system’s circuit boards, resulting in reduced cost, increased reliability and faster time to market. Full story...
Lattice's ispLeverCORE Connection program continues to grow with the addition of PLDA Applications (PLDA), the world’s largest supplier of PCI IP cores and derivatives. Full story...
The new Lattice ispClock5312S evaluation board provides a convenient platform for evaluating the ispClock5312S device, or helping to develop and program your own design. Full story...
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August 2007
