August 2006
Lattice offers the only 10GbE SPI4.2 solution for low cost FPGAs. This IPexpress™ User Configurable IP core is perfect for bridging functions like SPI3 to SPI4.2, SFI4 to SPI4.2 and many more.
The Lattice SPI4.2 solution targets the LatticeECP2™ FPGA and is the only programmable solution based on a low cost FPGA fabric that can operate at the full 10Gbps line rate. This speed is made possible by Lattice's unique sysIO™ interface structure, which contains pre-engineered elements designed to support the implementation of very fast, source synchronous interfaces such as DDR2 and SPI4.2. By delivering high-end FPGA features and performance in its low cost LatticeECP2 FPGA fabric, Lattice is able to provide the first FPGA-based SPI4.2 interface requiring less than $5.00 of FPGA logic in production volumes.
Lattice SPI4.2 System Level Context
Lattice's SPI4.2 solution is supported by Lattice's new IPexpress FPGA design tool module. Included as a standard feature in Lattice's ispLEVER® design tool suite, IPexpress significantly reduces design time by allowing IP parameterization and timing analysis on the designer's desktop.
An FPGA-based SPI4.2 solution provides system designers with a flexible way to support intelligent bridging functions interfacing with today's high-performance communications ASSPs. Until now, designers could implement full rate SPI4.2 bridges supporting complex packet flow and traffic management policies only on premium FPGA devices as low cost FPGAs could not support the I/O or logic speeds. This latest announcement vividly demonstrates Lattice's corporate philosophy of "More of the Best", combining the best 90nm FPGA silicon technology with the best FPGA architecture and features to deliver more performance at a more cost-effective price point.
The new SPI4.2 soft IP core requires less than 5000 FPGA look-up tables and can be implemented, therefore, along with other user logic in most LatticeECP2 family members from the LatticeECP2-12 through the largest member of the family, the LatticeECP2-70. The SPI4.2 core operates at interface speeds of up to 750Mbps while fulfilling all requirements of the SPI4.2 interface protocol.
The Optical Internetworking Forum (OIF) developed the System Packet Interface Level 4, Phase 2 (SPI-4.2) as a versatile interface for 10Gbps data transfer between a PHY and Link Layer device. SPI4.2 supports variable length packets and fixed cell sizes. LVDS signaling is used for data transfer across a 16-bit wide bus that utilizes source synchronous double edge clocking. Data is clocked at a minimum frequency of 311MHz for a minimim data rate of 622Mbps per lane.
Up to 256 logical ports are supported as the interface was designed for granularity at the STS-1 level for SONET/SDH applications (192 ports) and Fast Ethernet granularity for Ethernet applications (100 FE ports). The transmit and receive interfaces are completely independent which provides maximum design flexibility. Port status is communicated via separate Transmit and Receive Status interfaces.
SPI-4.2 Interface
SPI4.2 is a popular interface used on network processors, traffic managers, MACs, and framers. Typical applications include bridging functions as shown in the block diagram. Examples of bridging functions include: SPI3 to SPI4.2, SFI4 to SPI4.2 and parallel RIO to SPI4.2.
Line Card Application
© Lattice Semiconductor Corporation 2012
