August 2006
A list of recently published documents, including descriptions and ordering numbers.
On-line versions of these publications are available on the Lattice website at www.latticesemi.com. Some documents are also available in print. To order print versions, call your local Lattice representative or Lattice's Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
| Title | Description | Web | Order # | |
|---|---|---|---|---|
| General Information | ||||
| Lattice Automotive Product Brief | Overview of Lattice's automotive temperature range CPLDs. |  |
|
I0164A |
| MachXO™ Family Product Brief | Introduction to Lattice's low-cost, non-volatile, infinitely reconfigurable crossover PLD. | |
|
I0176C |
| ispClock™ Product Brief | Introduction to Lattice's In-System Programmable clock generator chips. | |
|
I0168D |
| ispPAC® Power Manager II Product Brief | Introduction to Lattice's second generation In-System Programmable power supply sequencing/monitoring chips. | |
|
I0178A |
| MachXO Standard Evaluation Board - Revision 001 User's Guide | Guidelines for operation of the MachXO Standard Evaluation Board, Revision 001. | |
— | — |
| Data Sheets and Handbooks | ||||
| LA-MachXO Automotive Family Data Sheet |
Full specifications for Lattice's low-cost, non-volatile, infinitely configurable crossover PLD now available in automotive temperature ranges. | |
— | — |
| LA-ispMACH 4000V Automotive Family Data Sheet |
Full specifications for Lattice's 3.3V In-System Programmable, SuperFAST™ high density PLDs now available in automotive temperature ranges. | |
— | — |
| ispClock5300S Family Data Sheet |
Full specifications for Lattice's single ended In-System Programmable, zero delay universal fanout buffer. | |
— | — |
| Technical Notes | ||||
| LatticeXP Tri-Speed Ethernet MAC Demo |
This demo uses a web server, entirely contained in a LatticeXP FPGA, to demonstrate the Tri-Speed Ethernet MAC IP Core. | |
— | — |
| Input Hysteresis in Lattice CPLD and FPGA Devices |
Several board design techniques for making slow input signals immune to input noise. | |
— | — |
| LatticeECP2 Soft Error Detection (SED) Usage Guide |
A hardware-based Soft Error Detect (SED) approach for LatticeECP2 FPGAs. | |
— | — |
| Electrical Recommendations for LatticeSC SERDES | Off-chip signal interface design and characteristics. Detailed information on interfacing requuirements for external high-speed devices with LVDS and LVPECL characteristics. | |
— | — |
| LatticeSC High Speed Backplane Measurements | Illustrates SERDES high-speed backplane capabilities through a series of laboratory tests. | |
— | — |
| Intellectual Property | ||||
| SPI4 IP Core User's Guide |
Detailed user's guides for Lattice's latest IP Core products. |
|
— | — |
| OBSAI RP3 User's Guide | |
— | — | |
| CPRI User's Guide | |
— | — | |
| DDR2 SDRAM Controller - Pipelined User's Guide | |
— | — | |
© Lattice Semiconductor Corporation 2012
