August 2006
Does the LatticeSC family provide embedded ASIC features similar to Lattice's FPSC family of devices?
The LatticeSC FPGA family combines a high-performance FPGA fabric, high-performance I/Os and large embedded RAM in an industry leading architecture. In addition, all LatticeSC devices also feature up to 32 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The flexiPCS™ logic can be configured to support numerous industry standard high-speed data transfer protocols. Each channel of flexiPCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial data transfers at data rates up to 3.8Gbps. The PCS logic in each channel can be configured to support an array of popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10Gbps or above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X specification), 1.02 or 2.04 Gbps Fibre Channel, PCI Express and Serial RapidIO. In addition, the protocol-based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface. Protocols requiring data rates above 3.8Gbps can be accommodated by dedicating either one pair or all four channels in one PCS quad block to one data link. One quad can support full-duplex serial data transfers at data rates up to 15.2Gbps. A single PCS quad can be configured to support 10Gbps Ethernet (with a fully compliant XAUI interface), 10Gbps Fibre Channel, and x4 PCI Express and 4x RapidIO. The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic. Each SERDES pin can also be independently configured to allow both high-speed and low-speed operation on the same SERDES pin for Serial Digital Video applications.
For more information on the LatticeSC family of devices, please consult the LatticeSC product page of the Lattice website.
How do I implement high speed generic DDR interface in LatticeECP2 devices?
The DDR registers in the LatticeECP2 I/O logic can be used to implement high-speed generic DDR interfaces. The DDR input and output registers support 1x and 2x gearing ratios. The gearing capability of the DDR registers allows interfacing to high speed DDR data. A basic 1x DDR element provides two FPGA side data bits for one I/O side data bit at the same clock rate. A 2x DDR element provides four FPGA side data bits for every I/O side data bit at half the clock rate. The gearing allows Muxing/Demuxing of the I/O data clocked with the high speed Edge Clock (ECLK) to the slower speed FPGA clock rate (SCLK). The table below shows how the gearing works.
| Data Path | Clock Frequency | Clock | Bus Width |
|---|---|---|---|
| I/O Pin | 200 MHz (I/O Clock) | ECLK (both edges) | 8 bits |
| Internal 1x Gearing | 200 MHz (FPGA Clock) | SCLK (rising edge) | 16 bits |
| Internal 2x Gearing | 100 MHz (FPGA Clock) | SCLK (rising edge) | 32 bits |
LatticeECP2 devices support Generic DDR interfaces using the following I/O Library elements:
The following figures show example waveforms for input and output DDR interfaces using a 2x gearing ratio.
Input Gearing Example
Output Gearing Example
My system runs from a primary 12V DC power supply that is used to distribute power to other DC/DC converters to generate 3.3V, 2.5V, 1.8V etc. I need to run the Power Manager II ispPAC-POWR1014A on a 3.3V rail but the 3.3V rail needs to be sequenced by the ispPAC-POWR1014 and used by other chip-sets on the board. How can I run a Power Manager device from a 12V supply?
Since there are multiple supplies and they need to be controlled and sequenced, a separate 3.3V supply is needed to run the POWR1014A. The designer could add another DC/DC converter that runs from the 12V main and generates 3.3V just for the Power Manager II. This way the 3.3V (POWR1014A) would come up as soon as the 12V went on and the other supplies could be controlled by the POWR1014A as needed. Sequencing, monitoring and control signals could come from the POWR1014A as soon as the device has been powered up and has gone through reset.
Another alternative is a low cost LDO. An even simpler solution is to build a Zener regulator. The simple Zener regulator uses a Zener diode to develop a voltage drop at a known value like 4.3V. This then drives a small NPN transistor to develop the voltage for the Power Manager, the voltage seen at the supply for the POWR1014A is (Vzener-Vbe), the voltage drop across the Zener diode minus the base-emitter drop of the transistor, setting the voltage around 3.6V to 3.7V. The supply range for POWR1014A is 2.8V to 3.96V.
The advantages of the method shown include both the low cost of the components and minimum board real estate. Discrete devices such as the Zener diode, resistor and transistor are available in very small surface mount packages and take up little board area. The current required for the POWR1014A is about 30mA plus any output sink current and can easily run from a small discrete regulator. The 12V rail can be monitored using a simple resistor divider and the POWR1014A VCC rail can be monitored as well.
The simple reliable circuit saves board space and has a very low cost.
© Lattice Semiconductor Corporation 2012
