August 2006
Lattice upgrades FPGA design software with 90nm FPGA device support and productivity enhancements for I/O planning and design with IP cores.
Version 6.0 and the related service pack (SP1) of ispLEVER software now provides support for Lattice's latest 90nm FPGA families and new features to improve design productivity across Lattice devices. These 90nm families include:
The new ispLEVER Design Planner integrates the two most common ispLEVER tools used to capture user objectives and visualize design implementations to more closely mirror the thought process and work flow of expert FPGA designers. The Design Planner's Spreadsheet View is used to define design parameters such as critical paths and timing objectives in a convienent tabular display. The Design Planner's Floorplan View supports detailed control over logic placement within a device and helps illustrate design connectivity. New features like the Assign Pins dialog ease I/O assignments by allowing to you to filter pins by functionality and validate an I/O plan before place and route.
ispLEVER Design Planner's Assign Pins Dialog Box
The new ispLEVER IPexpress™ flow significantly reduces design time by allowing IP parameterization and timing analysis on the designer's desktop. By configuring IP cores using the IPexpress flow, designers are able to simulate, place and route, generate netlists and run static timing analysis with their own logic and selected core parameters in real-time. In addition, a new hardware evaluation capability minimizes design risk by allowing free trial use of the cores prior to the purchase of an IP core license. IPexpress-supported functions include DDR, Ethernet, FIR, FFT, PCI and Reed-Solomon Encoder/Decoder.
The IPexpress web interface allows users to browse, download, and install new cores from the Lattice IP server independent of ispLEVER versions. New IPexpress cores will be released throughout the year.
IPexpress Graphical User Interface
Power estimation is an important requirement for all designs using today's high-performance FPGAs. Overall system power consumption is a key design constraint for many systems. In addition, exceeding the manufacturer's recommended operating temperatures can adversely affect the device's functionality, operating specifications or long-term reliability. Lattice's new Power Calculator in ispLEVER 6.0 SP1 has been greatly enhanced in this release to provide even more accurate power modeling of Lattice's latest FPGAs. If you haven't already, check-out the new Power Calculator - it's an easy path to power consumption peace-of-mind.
ispLEVER 6.0 SP1 Power Calculator
A new schematic design library for the ispLEVER Schematic Editor allows designers to develop gate-level circuits based on library elements from the ispLEVER FPGA Libraries Help System. The libraries contain standard Boolean gates, latches, flip-flops and I/O buffers compatible across all Lattice FPGA device families. The new FPGA Schematic and HDL Design Tutorial included in ispLEVER 6.0 provides design examples using a mixture of gate-level schematics modules generated by IPexpress, and RTL blocks to complete a design with the Schematic Editor. The new Lattice FPGA schematic library supports the LatticeECP2, LatticeECP™, LatticeEC™, LatticeSC, LatticeXP™ and MachXO™ families.
Lattice continues to work closely with third-party synthesis and simulation partners Mentor Graphics® and Synplicity® to provide designers with industry-leading solutions as a standard ispLEVER feature. All third-party tools have been updated with performance enhancements for Lattice FPGAs. Included in the ispLEVER design suite are Mentor Graphics' Precision® RTL synthesis version 2005c and ModelSim® simulator version 6.1d, and Synplicity's Synplify® synthesis version 8.5d.
© Lattice Semiconductor Corporation 2012
