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The Lattice SPI4.2 solution targets the LatticeECP2™ FPGA and is the only programmable solution based on a low cost FPGA fabric that can operate at the full 10Gbps line rate. This speed is made possible by Lattice's unique sysIO™ interface structure, which contains pre-engineered elements designed to support the implementation of very fast, source synchronous interfaces such as DDR2 and SPI4.2. Full story
Automotive versions of Lattice's MachXO™ Crossover Programmable Logic Devices and ispMACH™ 4000V CPLD devices have been characterized and qualified to meet the certification requirements of the AEC-Q100 standard as defined by the Automotive Electronics Council. Full story
Lattice has expanded the ispClock™5300S family of in-system programmable, zero-delay, single-ended buffer devices, with the production release of the ispClock5308S and ispClock5304S devices. Full story
Version 6.0 and the related service pack (SP1) of ispLEVER® software now provides support for Lattice's latest 90nm FPGA families and new features such as an updated Power Calculator to improve design productivity across Lattice devices. Full story
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August 2006
