August 2006

Signal Integrity and Crosstalk Analysis with Lattice IBIS Models

Learn how to get started with signal integrity and crosstalk analysis of PCB designs that utilize Lattice FPGAs.

PCB designers face signal integrity and crosstalk problems at high data rates. Manufacturing artifacts such as inconsistencies in dielectric properties or trace width and variation in circuit spacing can impact signal performance. The designer must carefully consider signal integrity issues such as deformation of electronic signals as they travel on the PCB, crosstalk, ground-bounce and simultaneously switching outputs (SSO). The net of this complex problem is that it is difficult to predict and design for maximum performance.

The Input/Ouput Buffer Information Specification (IBIS) is a method for FPGA manufacturers to provide I/O device characteristics to designers through voltage/current (V/I) data without disclosing proprietary circuit/process information. It can be thought of as a behavioral modeling specification suitable for transmission line simulation of digital systems. IBIS models developed by Lattice provide I/O parameters in analog terms and can be used to characterize I/V output curves, rising/falling transition waveforms, and package parasitic information of the device.

Lattice distributes IBIS models on a family-by-family basis from the IBIS download page of the Lattice website or on a design-by-design basis using the IBIS Model process of the ispLEVER Project Navigator.

Free IBIS tools from Mentor Graphics, HyperLynx Visual IBIS Editor and the Zuken information utility 'ibisinf' are helpful to review the IBIS models of your project.

HyperLynx Visual IBIS Editor