August 2006
One-hour webcasts available on the Lattice website.
Recent Lattice webcasts are available on demand from the Lattice website and are shown in the table below. These one-hour webcasts are presented by Lattice technical staff and may include software demonstrations and question and answer sessions. To view any of the webcasts, go to the webcasts section of the Lattice website and select your topics of interest.
| Seminar Title | Featured Product | Recording Date | Abstract |
|---|---|---|---|
| Optimizing VHDL Coding for More Efficient FPGA Synthesis | ispLEVER® Design Software | 6/14/06 | How to write VHDL code that will produce the most efficient implementation in FPGA devices. Covers detailed do's and don'ts of synthesis coding styles and illustrates the optimization differences with actual FPGA area and timing results. |
| Low-Cost Universal Power Management | ispPAC® Power Manager II Family | 5/24/06 | Power management schemes vary by design, requiring a unique set of ICs, transistors, resistors and capacitors. This seminar introduces a low-cost programmable solution which can be used across multiple designs. The power management functions are designed and verified in software, resulting in a cost-effective, quick-to-market solution that saves circuit board space and bill of material costs. |
| Pre-Engineered PCI Express Solutions with the LatticeSC™ FPGA | LatticeSC™ FPGA Family | 5/02/06 | With dedicated hard IP for PCI Express protocol logic, 3.8Gbps PCS and ample FPGA logic, the new 90nm LatticeSC FPGA makes your PCI Express implementation fast, easy and inexpensive. |
| WiMax Designs Made Simple with Parameterizable IP | Lattice Intellectual Property | 4/26/06 | Learn how to simplify your design and shorten design time with Lattice Intellectual Property (IP). This Web Seminar focuses on the implementation of a Wi-Fi application from start to finish using Lattice's IPexpress™ flow. |
| Designing 2Gbps Parallel I/O with the LatticeSC FPGA | LatticeSC FPGA Family | 4/12/06 | Learn how the new LatticeSC PURESPEED™ I/O architecture addresses system-level design concerns by delivering the highest performing and most feature-rich source synchronous I/Os on any FPGA family. |
| Low Cost, 90nm FPGA Addresses Field Update and Design Security Issues | LatticeECP2™ FPGA Family | 4/05/06 | Learn how to take advantage of advanced LatticeECP2 configuration options such as encrypted bitstream capability, multiple boot images and Lattice's TransFR™ technology to make your next design more secure and robust. |
© Lattice Semiconductor Corporation 2012
