August 2006

Art of Silicon Ports Multimedia Cores to Lattice FPGAs

New ispLeverCORE™ Connection Partner, Art of Silicon, ports JPEG IP cores to newest Lattice families.

Multimedia applications are part of a booming market and FPGA usage in these applications is steadily on the rise. As a result, there has been an increased demand for multimedia IP cores. To help fulfill this need, Lattice has announced the addition of Art of Silicon to the About ispLeverCORE™ Connection partnership. Art of Silicon has initially ported, optimized and tested image compression cores to the LatticeECP2™, LatticeSC™ and LatticeXP™ families of FPGA devices. Specifically, the four IP cores available today include:

• JPEG Encoder - Grayscale
• JPEG Encoder - Color
• JPEG Decoder - Grayscale
• JPEG Decoder - Color

These cores support baseline compliance to the ISO/IEC 10918-1 standard. Additionally, they support image sizes of 64k x 64k and 8 bits per pixel. Art of Silicon, based in Bristol, United Kingdom, with its in-depth multimedia expertise, will allow Lattice to provide high performance and competitive solutions to its customers.

For further information, visit the Art of Silicon website.