April 2011

Compression and Encryption IP Cores From Helion Technology for the LatticeECP3 FPGA Family

Lattice and Helion Technology have announced a portfolio of Compression and Encryption IP cores for the LatticeECP3 FPGA family. Helion Technology was first to market with numerous class-leading security solutions, with several years of proven IP core development experience and extensively-deployed solutions in real products. With these cores, designers can develop applications targeted at communications, industrial and military markets.

The following IP cores are supported on the LatticeECP3 FPGA family.

Helion Payload Compression System Cores: As network traffic increases, the need for compression increases to improve utilization of constrained channel bandwidth, thus making it ideal for use in Microwave Backhaul applications, Broadband Wireless Access for 802.16e (WiMAX), and potentially other Multi-Link Multi-In Multi-Out (MIMO) applications. The IP core is seamlessly scalable from 500Mbps to over 3Gbps in LatticeECP3, and may be used in typical networking applications at either Layer 2 or Layer 3. The IP core uses a very robust and mature implementation of the LZRW lossless compression algorithm.

• Payload Compression System

Helion LZRW Loss-Less Compression Cores: The Helion LZRW core is an excellent general purpose compression solution, requiring no external memory and supporting data rates over 500Mbps. The core is available in Compress only, Expand only, or combined Compress/Expand versions, and has been used to great effect by Helion customers in a broad range of applications in embedded systems.

• LZRW3 Data Compression Core

Helion Advanced Encryption Standard (AES): AES is pervasive and found in many standards, covering commercial, military and government applications. With over a decade of experience with AES, Helion offers a broad range of solutions carefully tailored to each requirement and engineered for optimal use in FPGAs. In each case, options allow the user to trade-off resources and performance to achieve an elegant and efficient solution. The supported IP cores include AES (Rijndael), Tiny AES, AES-GCM, AES-CCM and DES.

• AES: Fast AES Core
• AES: Standard AES Core
• AES: Tiny AES Core
• AES: AES-CCM Core
• AES: AES-GCM Core
• DES: High Performance DES and Triple-DES Cores

Helion Hash Cores: The Helion Fast Hash core family implements the NIST-approved SHA-1, SHA-256, SHA-384 and SHA-512 secure hash algorithms compliant to FIPS 180-3 and the legacy MD5 hash algorithm compliant to RFC1321. These high-performance, secure hash cores are available in single- or dual-mode versions and have been designed specifically for use in the LatticeECP3 FPGA family. Additionally, for resource-constrained implementations relative to performance, a super compact “Tiny” Hash core is also available that offers full multi-mode support plus a rich feature set.

• Hash: Fast Hash Core
• Hash: Tiny Hash Core

Helion Modular Exponentiation Cores: For accelerating public/private key protocols, the Helion Modular Exponentiation core offers an easy-to-use and highly-scalable solution. The core is available in several versions, each sharing an identical interface but differing in the number of clock cycles required to perform each operation. This allows the user to size an appropriate solution for any given requirement, trading off performance and logic area as needed and permitting easy up- or downgrades to end products.

• Modular Exponentiation Core

Helion Digital Video Broadcast (DVB) Common Scrambling Algorithm (CSA): Implements ETSI-specified DVB Common Scrambling Algorithm as used in Conditional access mechanism for MPEG-2 video streams for use in Pay-TV systems, adopted by the Digital Video Broadcasting consortium. Available as separate Scrambler and Descrambler cores.

• Common Scrambling Algorithm Cores