April 2010As more strict government power consumption regulations are applied to industry, traditional home and office appliances like LCD TVs, set top boxes (STBs), and multi-function printers (MFPs) are being scrutinized for ways to minimize standby or "phantom" power which refers to the power used while the product is performing no function. The International Energy Agency estimates that standby power produces 1% of the world's CO2 emissions. To put the figure into context, total air travel contributes less than 3% to global CO2 emissions.
To help ensure products are in compliance with the latest EnergyStar and EC Code of Conduct regulations, designers are seeking new ways to extend the time systems can remain in low-power modes of operation. A dedicated PLD resource can help coordinate power management for the entire system because the PLD delivers the flexibility for power optimization, as well as standby operation to implement complete system level standby power modes below one watt.
PLDs are applied to maximize the amount of circuitry that can be unpowered or placed in a standby/sleep mode as much as possible when the system is idle.
Clock gating is one of the power-saving techniques used on many synchronous circuits. To save power, clock gating support adds additional logic to a circuit to prune the clock tree, disabling portions of the circuitry so that its flip-flops do not change state. A CPLD coupled with an inexpensive crystal Pierce RC circuit can provide an automatic hardware clock gating method. The circuit below is an example implementation for a gated real time clock (RTC) source at 32.768 kHz, a clock commonly found in handheld devices like Smartphones.
Clock Distribution and Gating
Lattice provides application note AN8080 Using a Discrete Crystal as a PLD Clock Source with details on the discrete crystal circuit design.
One technical solution for the problem of reducing standby power is a smart electronic switch that cuts power when there is no load, or after some period of inactivity, and restores it immediately when required. PLDs are used with popular application chipsets to reduce standby power and minimize the time that key processors need to be powered on to detect system events. Power management is a feature of some electrical appliances, especially set top boxes, computers and computer peripherals such as monitors and printers, that turns off the power or switches the system to a low-power state when inactive.
Within the set top box architecture illustrated below, as program updates or subscription content is pushed from the headend to the user, the arrival can "wake up" the idle set top box when it is addressed. A low power CPLD like the ispMACH 4000ZE serves as a system sleep manager responding when Ethernet packets arrive, while keeping the majority of the appliance powered down or in a sleep state to minimize phantom power.
IP TV Set Top Box Wake On LAN Example
With initiatives being taken up around the world, low-power PLDs have emerged in a variety of roles to serve as smart energy efficiency switches to "wake" idle chip sets and when integrated with an inexpensive crystal can serve to gate clock networks.
Learn more about the ispMACH 4000ZE CPLD family and design resources like development kits and application notes in the links below.
© Lattice Semiconductor Corporation 2012
