April 2010The Marvell Alaska 88X2040 Quad transceiver is a fully-integrated SERDES device that incorporates four independent lanes, delivering high-speed bi-directional point-to-point baseband data transmission that supports cost-effective IEEE 802.3ae compliant 10-gigabit Ethernet and 10-gigabit Fibre Channel applications. It supports data rates up to 3.1875 Gbps and supports the 32-bit bi-directional 10-Gigabit Media Independent Interface (XGMII) with 8b10b ENDEC option, and the extended Auxiliary Unit Interface (XAUI). The 88X2040 performs the parallel-to-serial, serial-to-parallel conversion with integrated Time Base Generator (TBG) and Clock/Data Recovery Circuit (CDRC).
The award-winning LatticeECP3 FPGA family combines a high-performance FPGA fabric, high-performance I/Os and up to 16 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The PCS logic can be configured to support numerous industry-standard, high-speed serial data transfer protocols. Each channel of PCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial data transfer at data rates up to 3.2 Gbps. The PCS logic in each channel can be configured to support an array of popular data protocols including GbE/SGMII, XAUI, PCI Express, SRIO, CPRI, and Tri-rate SDI.
XAUI is a high-speed interconnect that offers reduced pin count and the ability to drive up to 20 inches of PCB trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b10b encoded serial lanes each operating at 3.125 Gbps and thus is capable of transferring data at an aggregate rate of 10 Gbps.
The Lattice XAUI IP core for LatticeECP3 FPGAs provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface (XGMII) devices. It implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solution.
The test setup for XAUI interoperability includes a Tyco Backplane (using the 16” HM-ZD slots), Two SMA to HM-ZD daughter cards to interface with the Marvell 88X2040 evaluation LB SMA board (with the 88X2040 device) and the LatticeECP3 Serial Protocol Board (with LFE3-95E 7FN1156CES device) as shown in the block diagram below.
Test Setup Block Diagram
The LatticeECP3 XAUI generator transmits CJPAT packets through the XAUI PCS soft IP and the LatticeECP3 XAUI PCS to the Marvell 88X2040 device. In the Rx direction, the LatticeECP3 SERDES recovers the packets from the Marvell 88X2040 device and the XAUI IP converts them into XGMII format. The XAUI checker then checks the received patterns.
The Marvell 88X2040 checks full protocol-compliant 10-gigabit Ethernet (10 Gbps) CJPAT packets at the XGMII interface. The 88X2040 also loops back the XGMII data back into the Tx direction. The 88X2040 device then transmits the packets back to the LatticeECP3 device.
The setup ran for approximately one hour and 40 minutes. Throughout the test, the Lattice/Marvell RX error counters remained at zero. At the end of the test, the LatticeECP3 XAUI Generator/Checker TX and Rx packet counter were identical in value, indicating the LatticeECP3 FPGA family is fully XAUI interoperable with the Marvell 88X2040 device. There were a total of 4,958,904,946 packets transferred across the system.
Board Connections
For more information on this interoperability, download TN1194, LatticeECP3 Marvell XAUI 10 Gbps Physical Layer Interoperability. For information on other interoperability tests please visit the Partners Solutions web page on the Lattice web site.
© Lattice Semiconductor Corporation 2012
