April 2009

Lattice Listens

Q: What can I do to prevent system disruption during PLD updates?  

A:  There are several options for preventing system disruption during PLD updates. They may be used independently or in conjunction with one another on some devices.

• Background Programming - On devices that have both on-chip Flash and SRAM, such as MachXO PLDs, the Flash can be updated while the SRAM continues to control the device behavior. Once complete, the SRAM can be reconfigured with the updated function on command or after a power cycle.
• Leave Alone I/O - With this capability, the boundary scan cells are used to capture the state of each I/O prior to entering a programming cycle. Control of each I/O then switches to the boundary scan cells holding the previous values, seamlessly maintaining this last state for the duration of the process. Once complete, control of the I/Os is switched to the updated design.
• TransFR - Transparent Field Reconfiguration combines the previous methods, providing a way to apply the new design updated in internal Flash memory to the active SRAM space while maintaining the I/O states throughout.

The diagram below shows how this sequence occurs. The first column shows normal operation in which the same configuration is held in both the SRAM and Flash.

In the second phase, a new configuration is loaded into the Flash, with the old configuration still in the SRAM. If a designer loads the configuration from the Flash directly into the SRAM, the outputs will go to some unpredictable values.

To prevent this from happening, the FPGA outputs are locked in the third phase. The user can control whether 0’s, 1’s or Z’s are held on the outputs. There is also a “leave alone” option where the driver will simply hold the last value that existed on that pin.

Phase four keeps the outputs locked while the SRAM is loaded with the new configuration. In the fifth and final stage, the device returns to normal operation without the outputs having to have been tristated.

The TransFR feature is available on MachXO, LatticeXP2 and LatticeXP devices.

To Learn More

For more information on TransFR, visit the TransFR Technology web page on the Lattice website. Also see the Field Update FPGAs While System Operates white paper.