April 2009

SOHO VOIP Solution: Intel/Lattice HSS-to-PCI Express Bridge

Lattice is pleased to announce the availability of a low-cost programmable PCI Express-to-High Speed Serial (HSS) bridge for the CAP12-120, a Small Office Home Office (SOHO) Voice Over IP (VOIP) platform running on Intel® architecture. This bridge design has been implemented in the award-winning LatticeECP2M FPGA. The solution utilizes the LatticeECP2M's low power, high-performance SERDES and a Lattice PCI Express Intellectual Property (IP) core. The system is targeted at the small office market (15-120 seats) and lowers the cost per port to new levels.

This system was announced by Intel at the VoiceCon 2008 conference and is being offered as a reference design from Intel. The database for this reference design is available from Intel and licensed at a very nominal charge.

The CAP12-120 design supports several types of I/O card functionality, from T1/E1 data in addition to traditional analog POTS phone connectivity.

The system is architected around a Celeron-based PC motherboard running Linux, with the LatticeECP2M FPGA connected to Intel’s I/O chipset. The analog phone lines are digitized using a SLIC card and the datastreams are sent to the Lattice FPGA. The Lattice FPGA aggregates and TDMs the traffic between the SLIC card and packetizes it into PCI Express data to the I/O chipset. Voice CODEC transcoding and echo cancellation is done in software (Trixbox)  with the Celeron and the PC sub-system.

Below is a block diagram of the system.

System-Level Block Diagram

The CAP12-120 design offers the following features:

• Dual High-Speed Serial (HSS) ports support multiple TDM bus fashions with programmable line clock speed up to 8.192 MHz (128 timeslots).
• The Expansion Bus can be configured as multiplexed or non-multiplexed address/data busses for Intel/Motorola bus cycles, with up to 16-bit data bus and 24-bit address bus, supporting outbound transfer.
• The Synchronous Serial Port (SSP) supports processor-initiated data transfer with 16 entries deep x 16 bits wide buffer on each direction. The read and write operation share the same PCI address. It seamlessly connects to a variety of external devices supporting TI SSP or Motorola SPI protocol.
• Boot SRAM-based FPGA from two different types of non-volatile media: SPI Flash memory and parallel Flash memory. Both methods support encryption, dual boot and field upgrading.
• Low-density and low pin-count preserves capacities for future expansions.
• Digital filtering and buffering design techniques applied to the HSS ports ensure a robust and stable serial interface.
• Embedded ASIC SERDES/PCS and Lattice-developed PCI Express IP core guarantees a quick and reliable PCI Express link.
• Available in a small-footprint 17x17 mm 256-ball fpBGA package.
• 1.2V core supply voltage.

To Learn More

To read more about the Intel/Lattice CAP12-120 solution, see the Lattice press release, Intel's Converged Application Platforms brochure and the DSP Design Line web site.