|
On April 28th, Lattice announced its new, ultra low power CPLD, the 1.8V ispMACH 4000ZE family. This second-generation in-system programmable CPLD family is ideal for low-power, high-volume portable applications, with typical standby current as low as 10µA.
Full story...
ispLEVER Design Tool Suite includes an industry-first SSO Analyzer for SERDES design and new, upgraded synthesis and simulation tools, making ispLEVER better and easier to use than ever before.
Full story...
Power Manager II devices deliver flexible, complex power management using any analog DC-DC converter. Full story...
Embedded high-speed SERDES channels in the LatticeECP2M FPGA enable support of the JESD204 serial ADC standard. Full story...
Lattice FPGAs and microcontroller IP create a quick, cost-effective solution for replacing existing microcontrollers while maintaining software compatibility. Full story...
|
Sign In
May 2008
