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Lattice has teamed with TM Associates to offer a complete complement of Verilog, VHDL and related courses. TM Associates has specialized in training for the electronic design industry for over 12 years and has trained thousands of people.
The following courses are available at Lattice in Hillsboro and San Jose. All courses are also available on-site at the customer’s location. To schedule on-site courses contact TM Associates at 888-656-4457.
For the current schedule see the events calendar.
Verilog Courses
Lattice FPGAs with Verilog - 3 days
Basic Level, 50% Lecture, 50% Labs
$1500
The Verilog hardware description language plays a key role in design flows for ASICs and FPGAs. It is increasingly important that people involved with hardware design have a background in this language and an awareness of the features introduced by IEEE Std 1364-201. This course provides a basic introduction to the main features of the Verilog language. The course will familiarize the student with the language and bridge the gap between the basic concepts in digital logic (schematics, Boolean equations, truth tables, etc.) and related constructs used in Verilog-based design flows. Several examples will illustrate language features, including an introduction to modeling styles suitable for synthesis and verification.
For complete information on the course visit www.tm-associates.com/Lattice_FPGAs_with_Verilog.htm
For the current schedule see the events calendar.
Verilog 2001 for Hardware Designers - 4 days
Basic Level, 50% Lecture, 50% Lab
$2000
The Verilog hardware description language plays a key role in design flows for ASICs and FPGAs. Yet many designers lack skill with this language. This course provides a comprehensive presentation of the main features of the Verilog language and the extensions introduced by Verilog 2001 (IEEE Std. 1364-2001). The course will bridge the gap between the designer's prior background in digital logic (schematics, Boolean equations, truth tables, state transition graphs, ASM charts) and related Verilog constructs used in modern design flows. Several examples (e.g., FIFO, three-state bus, synchronization across clock domains) will be used to illustrate language features, including an introduction to correct modeling styles for synthesis and verification. A comprehensive lab on the final day will reinforce the material by using a real-world design.
For complete information on the course visit www.tm-associates.com/vlog_4day.html
For the current schedule see the events calendar.
Advanced Verilog 2001 Coding Styles for Synthesis & Verification – 3 days
Advanced Level, 50% Lecture, 50% Lab
Staying competitive in today's ASIC/FPGA market means designing ICs with greater functionality, higher speed, and lower cost. Effective Verilog-2001 coding techniques can make all the difference between designs that meet tough synthesis targets and verification schedules, versus those requiring re-spins. The goal of this hands-on workshop is to enhance your mastery of Verilog language features which drive the synthesis tool and maximize verification productivity. Most of the material is tool-neutral, although case studies include results for popular ASIC/FPGA tools. Each key principle or coding insight is shown in the context of a realistic design situation. You'll be exposed to a wireless-telephony chip design, both in lectures and labs. Digital video and graphics applications are also explored. This course can be customized or condensed to meet the specific needs of your design team or available schedule.
For complete information on the course visit www.tm-associates.com/vlog_adv.html
For the current schedule see the events calendar.
Verilog Verification Methodology – 3 days
Intermediate Level, 50% Lecture, 50% Lab
Verification now takes 70% of the design cycle. To stay competitive in today's ASIC/FPGA market, you need to use the latest techniques to verify ICs. Creating a reusable test environment will allow you to create test cases and checkers quickly, and help you meet your project deadline. The goal of this hands-on class is to enhance your mastery of Verilog language, and use it to verify today's complex designs. Most of the material is tool-neutral, and verification techniques are limited in scope to the Verilog language itself-- no extra tools or languages to learn! This course can be customized or condensed to meet the specific needs of your design team or available schedule.
For complete information on the course visit www.tm-associates.com/vlog_ver.html
For the current schedule see the events calendar.
Verilog for Experienced VHDL Designers – 3 days
Intermediate/Advanced Level, 50% Lecture, 50% Lab
$1500
The learning curve for Verilog is not as steep as for VHDL, but it is longer. As a less restrictive language, Verilog has both strengths and weaknesses. This workshop covers the essential syntax of the Verilog language, the corresponding constructs with VHDL and alerts the users to some potential pitfalls. The workshop then accelerates into more advanced topics like coding to enhance speed and reduce area. Several larger case studies are included to highlight principles of coding for synthesis. Previews of SystemVerilog features are included, wherever significant future enhancements are anticipated (e.g. C-like structs to replace the need for faking records in Verilog).
For complete information on the course visit www.tm-associates.com/verilog_for_VHDL_designers.html
For the current schedule see the events calendar.
SystemVerilog for Verification Professionals – 3 days
Advanced Level, 50% lecture, 50% lab
In the semiconductor industry, faster time-to-market is the key to gaining a strong competitive advantage in the marketplace. Having a leading edge verification methodology is vital to achieving this. Our newest course offering SystemVerilog for Verification Professionals provides everything that you, the verification professional, need to create advanced constrained-random coverage-driven self-checking testbenches in the SystemVerilog language. From data types to program blocks and interfaces, to interprocess synchronization and communication, you will learn everything you need to create advanced SystemVerilog verification environments. This course details the advanced verification features of the language, focusing on constrained randomization, assertions, functional coverage, and other tools that facilitate an effective reusable verification environment. Throughout the course an example design is taken through the entire verification process, implementing a state-of-the-art, coverage-driven, constrained-random, assertion-based verification environment.
For complete information on the course visit www.tm-associates.com/SystemVerilog_for_Verification_Professionals.html
For the current schedule see the events calendar.
VHDL Courses
VHDL For Hardware Designers - 4 days
Basic Level, 50% Lecture, 50% Labs
VHDL is a feature-rich hardware description language, well suited to the synthesis and verification of complex system-on-a-chip ASICs and FPGAs. This course is a hardware-oriented VHDL primer for the digital design or verification engineer. Through real-world lecture insights and lab examples, participants in this comprehensive, hands-on course will learn to write synthesis-friendly, simulator-efficient code for progressively more complex logic blocks. They'll acquire confidence in utilizing the more powerful aspects of the language, while gaining mastery over its intricacies. The course focuses 70% on RTL code for synthesis, and 30% on testbench code for simulation.
For complete information on the course visit www.tm-associates.com/vhdl_4day.html
For the current schedule see the events calendar.
Advanced VHDL Coding Styles for Synthesis & Verification – 3 days
Advanced Level, 50% Lecture, 50% Labs
Synthesis and verification are key to successful ASIC and FPGA design. This course addresses a wide range of VHDL design areas integral to the design process. The course explores, in a tool independent format, methodology issues and examples, VHDL coding and modeling guidelines for synthesizable design and design verification. Lecture sessions are supported by multiple VHDL examples for each topic and are reinforced by application specific labs. Additional topics include creating synthesizable code for control, datapath, and FSM oriented designs. Creating verification environments and testbenches of varying complexity are fully explained. Additional topics include VHDL commenting guidelines, effective use of VHDL data types, and design for reuse issues.
For complete information on the course visit www.tm-associates.com/vhdl_adv.html
For the current schedule see the events calendar.
Related Courses
Perl - 3 days
Basic Level, 50% lecture, 50% lab
$1500
The Practical Extraction Report Language (Perl) is a popular and portable scripting language used by anyone who needs to extract and manipulate data coming from text files, log files, databases, pipes etc. Perl is extremely powerful and fast, but easier to learn than languages like C and Java. The student will be able to produce working and meaningful Perl programs upon completion of this course.
Benefits
Upon completion of this course, students will be able to:
- read, write and customize Perl scripts
- use Perl data types: scalars, arrays, and hashes
- use Perl operators to test and manipulate strings and numbers
- use programming constructs such as loops and decision making constructs
- use the power of regular expressions for extracting selected patterns in text
- open, close and test files and pipes
- modularize programs with subroutines
- debug Perl scripts
The course was developed and is taught by Ellie Quigley, author of “Perl by Example, 3rd Edition.”
For complete information on the course visit www.tm-associates.com/perl_3day.html
For the current schedule see the events calendar.
Advanced Perl - 3 days
Advanced Level, 50% lecture, 50% lab
The Practical Extraction Report Language (Perl) is a popular and portable scripting language used by anyone who needs to extract and manipulate data coming from text files, log files, databases, pipes etc. This course is a continuation of the Perl course. The student will be able to use and integrate Perl libraries and modules into his programs, use packages and modules from the standard Perl library, understand Perl references (pointers) for creating more complex data structures (hashes of hashes, multidimensional arrays, etc). Object oriented Perl will be introduced as well as dbm files (database management), and how to create user-friendly documentation.
The course was developed and is taught by Ellie Quigley, author of “Perl by Example, 3rd Edition.”
For complete information on the course visit www.tm-associates.com/advperl_3day.html
For the current schedule see the events calendar.
Tcl/Tk – 3 days
Basic Level, 50% lecture, 50% lab
$1500
Tcl (Tool Command Language) is a remarkably simple scripting language that’s easy to learn, yet powerful enough to implement large-scale, distributed applications. Whether you need to build a complex graphical user interface, create a network-enabled application, or develop a cross-platform program, Tcl can help you get the job done in less time than you thought possible. Additionally, the language’s support for Internet access, database access, and internationalization, as well as its stability and robustness, make it well-suited for enterprise-wide applications. The Tk extension to Tcl allows you to add a full-featured GUI to your application that will have a platform-native appearance on Windows, Unix, and Macintosh. This Tcl extension has proven so popular that it’s been ported as the standard GUI library for other scripting languages such as Perl and Python.
For complete information on the course visit www.tm-associates.com/TCL_TK.htm
For the current schedule see the events calendar.
Additional Courses
Other available courses include
- Unix Shell Programming – 4 days
- Linux Shell Programming – 4 days
- Unix Introduction – 3 days
- Javascript – 4 days
- Interprocess Communication with Tcl – 1 day
- Exploring Expect – 2 days
For complete information on these courses and current course schedule visit www.tm-associates.com
For the current schedule see the events calendar. |
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