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Topic ID Family Article Type Category Related To
Where can user find the device related information in Lattice Programmer? Like -... 5132 ispMACH 4000 faq Device Programming Diamond Programmer
Can we program an encrypted bitstream on the LatticeXP2 device without erasing the... 3316 LatticeXP2 faq Device Programming Configuration\/Programming
Does SMPTE SDI IP handle the ancillary data? 2305 LatticeECP3 faq Lattice IP\/Reference Design Tri-Rate SDI PHY
Non-root access installation issue:\r\nCustomer uses RHEL and downloaded SP2 from... 5450 MachXO2 faq Installation Linux
Does Lattice have performance data showing the throughput as a function of distance... 5442 ASSP-Wireless(Silicon Image) faq Lattice Evaluation Board
What is the \"TRC_DQS*\" in DDR3 SDRAM CONTROLLER IP?\r\n--------\r\nTRC_DQS0=1000\r\nT... 5435 LatticeECP5 faq Lattice IP\/Reference Design DDR3 SDRAM Controller
Is the active pixel in 720 x 480 and data type is YUV 422_8 is 720 or 1440 word count? 5434 CrossLink faq Lattice IP\/Reference Design
How to properly run RD1012 simulation using Diamond Software? 5432 MachXO2 faq Lattice IP\/Reference Design 8b\/10b Encoder\/Decoder
Why does there are still 10 single-ended RX lines even if I configure it to be 8 RX... 5428 CrossLink faq Lattice IP\/Reference Design IP\/Reference Design Inquiries
Why does the connection type is still \"pad-pin\"declared in Clarity even if the signal... 5424 CrossLink faq Implementation
Why are there ambiguities in FPGA-TN-02012 and FPGA-DS-02007 regarding PCN #02A-18? 5413 CrossLink faq Architecture IO
Can Crosslink device layout be implemented without blind vias? Can I get an example for... 5406 CrossLink faq Customer Board Design
What to do when you cannot generate 10MHz signal from 48MHz on PLL of XP2? 5400 LatticeXP2 faq Implementation IPExpress
Why does there is no any MIPI data after executing run simulation and an error occurred... 5399 CrossLink faq Simulation Aldec
For MachXO2, what is the condition of I\/O when powered down? 5393 MachXO2 faq Architecture Power
Why does the generated VHDL code does not contain any ports\tfor csi2\/dsi d-phy... 5389 CrossLink faq IntelliProp
How can ECP5 be internally access any unique number from inside it\'s own design? 5384 LatticeECP5 faq Lattice Evaluation Board
Customer has voltage in 2.8V range. Will that work for VCCAUX and VCCIO2 for Crosslink... 5381 CrossLink faq Other
What software should I use for syn_multstyle attribute? 5380 iCE40 UltraPlus faq Architecture DSP
In Mixel PLL, how does CM, CN and CO declared in the verilog parameters interpreted and... 5376 CrossLink faq Lattice IP\/Reference Design