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Topic ID Family Article Type Category Related To
Is BT656 format a valid input format for Deinterlacer IP? 3041 Other FPGA faq Lattice IP\/Reference Design Interleaver\/De-interleaver
What is the meaning of tags_in and tags_out signals? 3039 Other FPGA faq Lattice IP\/Reference Design Color Space Converter
How to connect the terminations for address, control and data lines for Double Data... 3026 LatticeECP3 faq Customer Board Design Schematic Review
Why do I see a short (150ns or longer) logic zero glitch on my Power Manager Supervisor... 2945 Power Manager II faq Customer Board Design Board Debug
Will the \"PRIVATE\" instructions in BSDL file have any impact on my BSCAN test? Do I... 2944 All Devices faq Device Modeling BSDL
What are the Linux environment variables and their values needed to run Multiple PAR... 2739 All Devices faq Implementation PAR
Why do I get error messages when running ispVME? 2732 All Devices faq Device Programming ispVM Embedded
Why is that in a mixed language designs, the top level signals are listed as nets not... 2729 All FPGA faq Debugging Reveal
In the Place and Route TRACE report, where can I see the results of changes made in the... 2724 LatticeECP3 faq Implementation Trace
Why does my LatticeECP2M Input DDR interface pass INPUT_SETUP preference in the Lattice... 2720 LatticeECP2\/M faq Architecture Generic DDR
Can my VCCIO output spec, for instance, use 3.3V at LVDS25 banks? 2716 All Devices faq Architecture IO
What are the programming modes available in LatticeiCE40 device? 2714 iCE40 faq Device Programming Configuration\/Programming
User MCS file translated from JED file by \u201CUniversal File Writer\u201D  doesn\'t... 2696 MachXO2 faq Device Programming ispVM System
Does Lattice recommend special handling of the CSSPIN pin for FPGA\'s configured via... 2677 All FPGA faq Device Programming Configuration\/Programming
Can a output enable signal be used for 7:1 LVDS(Low Voltage Differential Signalling)... 2676 LatticeECP3 faq Architecture IO
Why do I get a netsanitycheck Place and Route (PAR) error when a MUX drives the clock... 2657 LatticeECP3 faq Implementation PAR
What programming support is available for LatticeXO2 SSPI and I2C with the download cable? 2651 MachXO2 faq Device Programming Cables
We were attempting to reprogram the MachXO2 device via I2C interface from the processor... 2640 MachXO2 faq Device Programming Embedded Programming
Why is some logic in a sub-module not packed into the group after Place and Route (PAR)... 2612 LatticeECP3 faq Implementation Timing Closure
What does \"potential circuit loops found in timing analysis\" in trace report mean? 2592 LatticeECP3 faq Implementation Trace