Data Center Systems - Servers

Simplify control logic, security, and power and thermal management

First-On, Last-Off Solutions for Main Boards – Non-volatile, instant-on, lowest cost per I/IO, feature-rich MachXO3 FPGA family offers a wide range of single, dual, quadruple and 8-Socket CPU boards for Server, Storage and networking systems.

Small Form-Factor, Low-Cost Options for Hot-Swappable Backplane Applications – MachXO2 products available in TQFP and QFN packages provide lowest cost to manufacture options for auto-configure HDD, SSD and NVMe drives.

Reduce telemetry and CPLD cost, Routing Congestion and BOM – Integrate voltage, current and temperature monitoring and measurement functions of hardware management logic using L-ASC10. In addition, the real-time fault logging capability simplifies hardware debug.

Block Diagram

Rack Optimized Server

  • Control PLD
  • Interposer Controller for HDD/NVMe
  • Host Bus Adapter Controller
  • Control PLD and ASC
  • BIOS, BMC Firmware Validation
  • LPC to SPI Bridge for TPM in China on Purley Reference Design
  • Various Riser Cards
  • I2C Buffer Between CPU & DDR

Example Solutions

Control PLD

  • Power and reset sequencing, thermal management
  • Out-of-band signaling aggregation including 1V signals from CPU
  • Glue logic (SPI, I2C, UART, GPIO, SGPIO, fan controller, debug port, JTAG Mux, etc.)
  • Modify algorithms without power-cycling using hitless updates

Hot Swappable HDD/FD/ NVMe Drive Backplane Controller

  • Auto selection of control port from I2C, SGPIO between HDD/FD/NVMe drives
  • Scalable solution from 2 drives to 24 drives
  • Automatic color LED/ monochrome LED drive support
  • On-chip Flash and EBR for FRU data store

Host Bus Adapter Logic Integration

  • Integrate SGPIO and other out-of-band signaling
  • Power/reset sequencing and other control PLD functions, fast supply fault detect, initiate status save
  • On-chip Flash for fault logging, LED drives
  • In-system update through I2C with hitless I/O support

ASC to Control PLD

  • Reduce the number of I2C buffers/Mux
  • No external ADC needed
  • Reduce the number of temperature sense ICs
  • Reliable power-down sequencing
  • Reduced circuit board congestion

BIOS and BMC Firmware Authentication

  • Hardware root-of-trust security
  • Validates the BIOS and BMC firmware using elliptic curve signature authentication
  • Manages automatic golden image switchover in the case of compromised active image
  • Incorruptible in-system

LPC to SPI Bridge for TPM

  • Bridge between a single PCH interface and multiple TPM module interface
  • Compatible with wide range of operating frequencies at ingress and egress ports

I2C Buffer Integration

  • Multiple I2C buffers (PCA9617) for voltage level translation (CPU 1.05V to DDR4 1.2V)
  • Level translation for out-of-band 1V I/O signals from CPU
  • Multiple I2C Muxes
  • Multiple I2C GPIOs

Design Resources

Programmable Logic Development Kits & Boards
  Provider MachXO2 MachXO3 Platform Manager 2
L-ASC10 Breakout Board Lattice    
MachXO2 Breakout Board Lattice    
MachXO2 Control Development Kit Lattice    
MachXO3LF Starter Kit Lattice    
Platform Manager 2 Development Kit Lattice    


Quality & Reliability

Reference Material to Help Answer Your Questions