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  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • Single Wire Aggregation

    Reference Design

    Single Wire Aggregation

    Use a low-cost FPGA to aggregate multiple data streams such as I2C, UART, I2S and GPIO in TDM fashion, transmit a over single wire, and de-aggregate.
    Single Wire Aggregation
  • Single Wire Aggregation Demo / Development Board

    Board

    Single Wire Aggregation Demo / Development Board

    Use the world’s smallest form factor FPGAs to aggregate multiple data streams such as I2C, I2S and GPIO in TDM fashion, transmit over single wire, and de-aggregate.
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Master and Slave – Simple Write and Read

    Demo

    Soft I2C Master and Slave – Simple Write and Read

    Demonstrates the operation of an I2C Master and Slave doing simple write and read of data.
    Soft I2C Master and Slave – Simple Write and Read
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  • SPI Slave IP Core

    IP Core

  •  I2C Slave IP Core

    IP Core

    I2C Slave IP Core

    Interfaces to an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
     I2C Slave IP Core
  • I2C Master IP Core

    IP Core

    I2C Master IP Core

    Controls an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
    I2C Master IP Core
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.
    UART 16550 IP Core
  • PCI Express Endpoint Core

    IP Core

    PCI Express Endpoint Core

    Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer
    PCI Express Endpoint Core
  • iCE40 UltraPlus I2S IP

    IP Core

    iCE40 UltraPlus I2S IP

    Customize and control an I2S bus - Transmit/Receive from 16 to 32 bits.
    iCE40 UltraPlus I2S IP
  • Scatter-Gather DMA Controller

    IP Core

    Scatter-Gather DMA Controller

    Implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability
    Scatter-Gather DMA Controller
  • UART - WISHBONE Compatible

    Reference Design

    UART - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART - WISHBONE Compatible
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