Lattice Solutions

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Providers
  • CSI-2/DSI D-PHY Receiver

    IP Core

    CSI-2/DSI D-PHY Receiver

    Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Receiver
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • iCE40 UltraPlus MDP

    Board

    iCE40 UltraPlus MDP

    Evaluation and development board with 4 iCE40 UltraPlus FPGAs, loaded with mobile applications interfaces (camera, microphones, display, accelerometer, etc)
    iCE40 UltraPlus MDP
  • Graphics Acceleration

    Reference Design

    Graphics Acceleration

    Enables a processor to save power in sleep mode while the low-power iCE40 UltraPlus drives a mobile DSI display, and monitors for wake-up signals.
    Graphics Acceleration
  • MIPI DSI Receive Bridge

    Reference Design

    MIPI DSI Receive Bridge

    Allows an AP (Application Processor) or other DSI source to interface to a non-DSI (such as LVDS) display. Up to 4 data lanes at 900 Mbps per lane
    MIPI DSI Receive Bridge
  • iCE40 Ultra Wearable Development Platform

    Board

    iCE40 Ultra Wearable Development Platform

    Peripheral and sensor-rich development platform with iCE 40 Ultra and MachXO2 in a wearable watch form factor.
    iCE40 Ultra Wearable Development Platform
  • 1 Input to 1 Output MIPI DSI Display Interface Bridge

    IP Core

    1 Input to 1 Output MIPI DSI Display Interface Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. MIPI DSI to MIPI DSI pass through for updated DCS config, scaling / cropping, or as a redriver.
    1 Input to 1 Output MIPI DSI Display Interface Bridge
  • 1 Input to 2 Output MIPI DSI Display Splitter Bridge

    IP Core

    1 Input to 2 Output MIPI DSI Display Splitter Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Expands the number of display interfaces supported by an Application Processor.
    1 Input to 2 Output MIPI DSI Display Splitter Bridge
  • 1:2 MIPI DSI Display Interface Bandwidth Reducer

    IP Core

    1:2 MIPI DSI Display Interface Bandwidth Reducer

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Bridges an input video stream into two streams or one lower-resolution stream.
    1:2 MIPI DSI Display Interface Bandwidth Reducer
  • MIPI DSI to OpenLDI LVDS Display Interface Bridge

    IP Core

    MIPI DSI to OpenLDI LVDS Display Interface Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Bridges MIPI DSI data to an OpenLDI/LVDS display.
    MIPI DSI to OpenLDI LVDS Display Interface Bridge
  • MIPI DSI to RGB Display Interface Bridge

    IP Core

    MIPI DSI to RGB Display Interface Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Bridges MIPI DSI data to an RGB/CMOS display.
    MIPI DSI to RGB Display Interface Bridge
  • OpenLDI LVDS to MIPI DSI Display Interface Bridge

    IP Core

    OpenLDI LVDS to MIPI DSI Display Interface Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Bridges OpenLDS LVDS data to a MIPI DSI display.
    OpenLDI LVDS to MIPI DSI Display Interface Bridge
  • RGB to MIPI DSI Display Interface Bridge

    IP Core

    RGB to MIPI DSI Display Interface Bridge

    Archived IP - Use newer Modular MIPI/D-PHY IP for this function. Bridges parallel RGB data to MIPI DSI displays.
    RGB to MIPI DSI Display Interface Bridge
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