Lattice Solutions

Everything you need to quickly and easily complete your design

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Providers
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
    RISC-V MC CPU IP Core
  • ECP5 Evaluation Board

    Board

    ECP5 Evaluation Board

    Evaluation and development for ECP5-5G FPGA - 85K LUTs. Includes generous IO access and easy expansion to PMOD, Arduino, RaspberryPI, SERDES interface and more
    ECP5 Evaluation Board
  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • MachXO3D Breakout Board

    Board

    MachXO3D Breakout Board

    Small low-cost board with generous access to MachXO3D FPGA IO for general purpose evaluation and development
    MachXO3D Breakout Board
  • MachXO3D Development Board

    Board

    MachXO3D Development Board

    General purpose evaluation and development for MachXO3D with generous IO access and multiple expansion connectors RaspberryPi, Arduino, Lattice Versa, and more.
    MachXO3D Development Board
  • AHB-Lite Interconnect Module

    IP Core

    AHB-Lite Interconnect Module

    Propel IP Module: Fully parameterized interconnect for AHB-Lite systems - bus widths of 8 to 1024 bits, address widths up to 32 bits, 32 masters and 32 slaves.
    AHB-Lite Interconnect Module
  • AHB-Lite to APB Bridge Module

    IP Core

    AHB-Lite to APB Bridge Module

    Propel IP Module: Bridges high-speed AHB-lite to low-power APB. Data bus widths up to 32 bits. Address width up to 32 bits.
    AHB-Lite to APB Bridge Module
  • EFB Module

    IP Core

    EFB Module

    Propel IP Module: Implements the Embedded Function Block (EFB) in MachXO3D, including I2C, Configuration Blocks and User Flash Memory with an APB Interface.
    EFB Module
  • System Memory Module

    IP Core

    System Memory Module

    Propel IP Module: Configures Embedded Block RAMs or Distributed Memory interfaces and connects to the AHB-Lite bus.
    System Memory Module
  • UART IP Core

    IP Core

    UART IP Core

    Propel IP Module: Similar to NS16450 UART for serial communication supporting RS-232.
    UART IP Core
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
  • SPI Master IP Core

    IP Core

    SPI Master IP Core

    Communicates with external SPI slave devices. Configurable data width, FIFO Tx/Rx depth, polarity, clocking modes and memory interface.
    SPI Master IP Core
  • SPI Slave IP Core

    IP Core

  •  I2C Slave IP Core

    IP Core

    I2C Slave IP Core

    Interfaces to an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
     I2C Slave IP Core
  • I2C Master IP Core

    IP Core

    I2C Master IP Core

    Controls an I2C bus. Supports 7-bit and 10-bit addressing mode with programmable SCL frequency. Standard, Fast and Fast-mode plus support - up to 1 Mbit/s
    I2C Master IP Core
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.
    UART 16550 IP Core
  • ECP5 Versa Development Kit

    Board

    ECP5 Versa Development Kit

    Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.
    ECP5 Versa Development Kit
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